参数资料
型号: ISL6308CRZ
厂商: Intersil
文件页数: 14/28页
文件大小: 0K
描述: IC CTRLR PWM 3PHASE BUCK 40-QFN
标准包装: 500
应用: 控制器,DDR
输入电压: 5 V ~ 12 V
输出数: 1
输出电压: 0.6 V ~ 2.3 V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 40-VFQFN 裸露焊盘
供应商设备封装: 40-QFN(6x6)
包装: 管件
ISL6308
Advanced Adaptive Zero Shoot-Through Deadtime
VDIFF
Control (Patent Pending)
+
V OFS
-
R 1
VREF
E/A
The integrated drivers incorporate a unique adaptive
deadtime control technique to minimize deadtime, resulting
in high efficiency from the reduced freewheeling time of the
lower MOSFET body-diode conduction, and to prevent the
FB
I OFS
upper and lower MOSFETs from conducting simultaneously.
This is accomplished by ensuring either rising gate turns on
its MOSFET with minimum and sufficient delay after the
other has turned off.
During turn-off of the lower MOSFET, the PHASE voltage is
monitored until it reaches a -0.3V/+0.8V trip point for a
forward/reverse current, at which time the UGATE is
-
1.5V
released to rise. An auto-zero comparator is used to correct
+
+
the r DS(ON) drop in the phase voltage preventing false
R OFS
OFS
GND
ISL6308
-
GND
0.5V
VCC
detection of the -0.3V phase level during r DS(ON) conduction
period. In the case of zero current, the UGATE is released
after 35ns delay of the LGATE dropping below 0.5V. During
the phase detection, the disturbance of LGATE falling
transition on the PHASE node is blanked out to prevent
FIGURE 8. POSITIVE OFFSET OUTPUT VOLTAGE
PROGRAMMING
VDIFF
falsely tripping. Once the PHASE is high, the advanced
adaptive shoot-through circuitry monitors the PHASE and
UGATE voltages during a PWM falling edge and the
subsequent UGATE turn-off. If either the UGATE falls to less
-
V OFS
+
R 1
VREF
E/A
than 1.75V above the PHASE or the PHASE falls to less than
+0.8V, the LGATE is released to turn on.
Internal Bootstrap Device
I OFS
VCC
FB
All three integrated drivers feature an internal bootstrap
Schottky diode. Simply adding an external capacitor across
the BOOT and PHASE pins completes the bootstrap circuit.
The bootstrap function is also designed to prevent the
bootstrap capacitor from overcharging due to the large
negative swing at the PHASE node. This reduces voltage
stress on the boot to phase pins.
C BOOT_CAP ≥ --------------------------------------
Δ V BOOT_CAP
R OFS
OFS
ISL6308
+
-
GND
0.5V
-
1.5V
+
VCC
The bootstrap capacitor must have a maximum voltage
rating above PVCC + 5V and its capacitance value can be
chosen from Equation 11:
Q GATE
(EQ. 11)
Q GATE = --------------------------------- ? N Q1
FIGURE 9. NEGATIVE OFFSET OUTPUT VOLTAGE
PROGRAMMING
Once the desired output offset voltage has been determined,
use the following formulas to set R OFS :
For Positive Offset (connect R OFS to GND):
Q G1 ? PVCC
V GS1
where Q G1 is the amount of gate charge per upper MOSFET
at V GS1 gate-source voltage and N Q1 is the number of
control MOSFETs. The Δ V BOOT_CAP term is defined as the
R OFS = --------------------------
0.5 ? R 1
V OFFSET
For Negative Offset (connect R OFS to VCC):
(EQ. 9)
allowable droop in the rail of the upper gate drive. Figure 10
shows the boot capacitor ripple voltage as a function of boot
capacitor value and total upper MOSFET gate charge.
R OFS = --------------------------
1.5 ? R 1
V OFFSET
14
(EQ. 10)
FN9208.4
September 30, 2008
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