参数资料
型号: ISL6308CRZ
厂商: Intersil
文件页数: 12/28页
文件大小: 0K
描述: IC CTRLR PWM 3PHASE BUCK 40-QFN
标准包装: 500
应用: 控制器,DDR
输入电压: 5 V ~ 12 V
输出数: 1
输出电压: 0.6 V ~ 2.3 V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 40-VFQFN 裸露焊盘
供应商设备封装: 40-QFN(6x6)
包装: 管件
ISL6308
to VSEN pin to set the output voltage level as shown in
Figure 6. This method is good for generating voltages up to
circuitry that controls voltage regulation is illustrated in
Figure 6.
2.3V (with the REF voltage set to 1.5V).
For this case, the output voltage can be obtained as follows:
V OUT = V REF ± V OFST – V DROOP
(EQ. 5)
V OUT = V REF ? ---------------------------------- ? + V OFS – V DROOP
R
( R S1 + R P1 )
P1
(EQ. 4)
EXTERNAL CIRCUIT
R 2 C 1
COMP
ISL6308 INTERNAL CIRCUIT
It is recommended to choose resistor values of less than
500 Ω for R S1 and R P1 resistors in order to get better output
voltage DC accuracy.
TABLE 1. ISL6308 DAC VOLTAGE SELECTION TABLE
DAC
REF
C REF
VID DAC
+
REF1
0
0
1
1
Voltage Regulation
REF0
0
1
0
1
VDA (V)
0.600
0.900
1.200
1.500
R 1
+
V OFS
-
+
V OUT
R S1
FB
VDIFF
VSEN
R P1
I OFS
-
V COMP
ERROR AMPLIFIER
+
+
In order to regulate the output voltage to a specified level, the
ISL6308 uses the integrating compensation network shown in
Figure 6. This compensation network insures that the steady
state error in the output voltage is limited only to the error in
-
-
RGND
DROOP
-
-
DIFFERENTIAL
REMOTE-SENSE
AMPLIFIER
the reference voltage (output of the DAC or the external
V DROOP
voltage reference) and offset errors in the OFS current
+
IREF
source, remote sense and error amplifiers. Intersil specifies
the guaranteed tolerance of the ISL6308 to include the
combined tolerances of each of these elements, except when
an external reference or voltage divider is used, then the
C SUM
ICOMP
ISUM
+
ISENSE
AMP
-
tolerances of these components has to be taken into account.
The ISL6308 incorporates an internal differential remote
sense amplifier in the feedback path. The amplifier removes
the voltage error encountered when measuring the output
voltage relative to the controller ground reference point,
resulting in a more accurate means of sensing output voltage.
Connect the microprocessor sense pins to the non-inverting
input, VSEN, and inverting input, RGND, of the remote-sense
amplifier. The droop voltage, VDROOP, also feeds into the
remote-sense amplifier. The remote-sense output, VDIFF, is
therefore equal to the sum of the output voltage, VOUT, and
the droop voltage. VDIFF is connected to the inverting input of
the error amplifier through an external resistor.
The output of the error amplifier, V COMP , is compared to the
sawtooth waveform to generate the PWM signals. The PWM
signals control the timing of the Internal MOSFET drivers
and regulate the converter output so that the voltage at FB is
equal to the voltage at REF. This will regulate the output
voltage to be equal to Equation 5. The internal and external
12
FIGURE 6. OUTPUT VOLTAGE AND LOAD-LINE
REGULATION WITH OFFSET ADJUSTMENT
FN9208.4
September 30, 2008
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