参数资料
型号: ISL6308CRZ
厂商: Intersil
文件页数: 6/28页
文件大小: 0K
描述: IC CTRLR PWM 3PHASE BUCK 40-QFN
标准包装: 500
应用: 控制器,DDR
输入电压: 5 V ~ 12 V
输出数: 1
输出电压: 0.6 V ~ 2.3 V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 40-VFQFN 裸露焊盘
供应商设备封装: 40-QFN(6x6)
包装: 管件
ISL6308
Electrical Specifications
Recommended Operating Conditions, Unless Otherwise Specified. Parameters with MIN and/or MAX limits are
100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are
not production tested. (Continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
ERROR AMPLIFIER
DC Gain (Note 3)
Gain-Bandwidth Product (Note 3)
Slew Rate (Note 3)
Maximum Output Voltage
Minimum Output Voltage
R L = 10k to ground
C L = 100pF, R L = 10k to ground
C L = 100pF, Load = ±400μA
VCC = 5V; Load = 1mA
Load = -1mA
-
-
-
3.90
0.6
96
20
8
4.20
0.85
-
-
-
4.60
1.0
dB
MHz
V/μs
V
V
REMOTE SENSE DIFFERENTIAL AMPLIFIER
Input Bias Current (VSEN)
Bandwidth (Note 3)
Slew Rate (Note 3)
(VSEN = 1.5V)
49
-
-
55
20
8
60
-
-
μA
MHz
V/μs
OVERCURRENT PROTECTION
OCSET Trip Current
93
100
107
μA
OCSET Accuracy
ICOMP Offset
OC comparator offset (OCSET and ISUM Difference)
ISEN amplifier offset
-5
-5
0
0
5
5
mV
mV
PROTECTION
Undervoltage Threshold
Undervoltage Hysteresis
Overvoltage Threshold while IC Disabled
Overvoltage Threshold
VSEN falling
VSEN rising - VSEN falling
VSEN rising
80
2
1.62
DAC +
82
3
1.67
DAC +
84
4
1.72
DAC +
%VID
%VID
V
V
125mV
150mV
175mV
Overvoltage Hysteresis
Open Sense-Line Protection Threshold
VSEN rising - VSEN falling
IREF Rising and Falling
75
VDIFF
100
VDIFF +
125
VDIFF
mV
V
+ 0.9V
1V
+ 1.1V
OVP Output High Drive Voltage
PGOOD Output Low
I OVP = 50mA, VCC = 5V
VCC = 5V; 1k Ω resistor to VCC
2.2
0
3.8
0.2
4.4
0.4
V
V
SWITCHING TIME
UGATE Rise Time (Note 3)
LGATE Rise Time (Note 3)
UGATE Fall Time (Note 3)
LGATE Fall Time (Note 3)
UGATE Turn-On Non-overlap (Note 3)
LGATE Turn-On Non-overlap (Note 3)
t RUGATE; V PVCC = 12V, 3nF Load, 10% to 90%
t RLGATE; V PVCC = 12V, 3nF Load, 10% to 90%
t FUGATE; V PVCC = 12V, 3nF Load, 90% to 10%
t FLGATE; V PVCC = 12V, 3nF Load, 90% to 10%
t PDHUGATE ; V PVCC = 12V, 3nF Load, Adaptive
t PDHLGATE ; V PVCC = 12V, 3nF Load, Adaptive
-
-
-
-
-
-
26
18
18
12
10
10
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
GATE DRIVE RESISTANCE (Note 4)
Upper Drive Source Resistance
Upper Drive Sink Resistance
Lower Drive Source Resistance
Lower Drive Sink Resistance
V PVCC = 12V, 150mA Source Current
V PVCC = 12V, 150mA Sink Current
V PVCC = 12V, 150mA Source Current
V PVCC = 12V, 150mA Sink Current
1.25
0.9
0.85
0.60
2.0
1.6
1.4
0.94
3.0
3.0
2.2
1.35
Ω
Ω
Ω
Ω
OVER-TEMPERATURE SHUTDOWN
Thermal Shutdown Setpoint (Note 4)
Thermal Recovery Setpoint (Note 4)
-
-
160
100
-
-
°C
°C
NOTES:
3. Limits should be considered typical and are not production tested.
4. Limits established by characterization and are not production tested.
6
FN9208.4
September 30, 2008
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