参数资料
型号: ISL6308CRZ
厂商: Intersil
文件页数: 17/28页
文件大小: 0K
描述: IC CTRLR PWM 3PHASE BUCK 40-QFN
标准包装: 500
应用: 控制器,DDR
输入电压: 5 V ~ 12 V
输出数: 1
输出电压: 0.6 V ~ 2.3 V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 40-VFQFN 裸露焊盘
供应商设备封装: 40-QFN(6x6)
包装: 管件
ISL6308
Overvoltage Protection
The ISL6308 constantly monitors the difference between the
VSEN and RGND voltages to detect if an overvoltage event
occurs. Before, and during soft-start, while the DAC/REF is
ramping up, the overvoltage trip level is V OVP ; upon
successful soft-start, the overvoltage trip level changes to
V OVP_rise (typically REF+150mV, see Table Electrical
Specifications on page 5). Should an OVP event be
triggered for either case, the threshold hysteresis is 100mV
(typical) below its trip point, as sensed at the VSEN pins.
Actions are taken by the ISL6308A to protect the load when
an overvoltage condition occurs, until the output voltage falls
back within set limits.
At the inception of an overvoltage event, all LGATE signals
are commanded high, and the PGOOD signal is driven low.
This causes the controller to turn on the lower MOSFETs
and pull the output voltage below a level that might cause
damage to the load. The LGATE outputs remain high until
VDIFF falls to within the overvoltage limits explained above.
The ISL6308 will continue to protect the load in this fashion
as long as the overvoltage condition recurs.
During an OVP event, the OVP pin is pulled high and
PGOOD is pulled low. In addition to the OVP pin behavior,
the normal control loop behavior commands all LGATE
signals high as soon as the output voltage strays higher than
the set point, essentially protecting against OVP events long
before the OVP pin is triggered. Thusly, the OVP output is a
duplicate method of protection, allowing the user to
implement secondary measures of protection for cases
where normal circuit behavior is insufficient, or an additional
level of protection is desired. The ISL6308 continues to
protect the output in the fashion described for as long as the
cuts off. For complete protection, the low side MOSFET
should have a gate threshold well below the maximum
voltage rating of the load/microprocessor.
In the event that during normal operation the PVCC or VCC
voltage falls back below the POR threshold, the pre-POR
overvoltage protection circuitry reactivates to protect from
any more pre-POR overvoltage events.
Open Sense Line Protection
In the case that either of the remote sense lines, VSEN or
GND, become open, the ISL6308 is designed to detect this
and shut down the controller. This event is detected by
monitoring the voltage on the IREF pin, which is a local
version of V OUT sensed at the outputs of the inductors.
If VSEN or RGND become opened, VDIFF falls, causing the
duty cycle to increase and the output voltage on IREF to
increase. If the voltage on IREF exceeds “VDIFF+1V”, the
controller will shut down. Once the voltage on IREF falls
below “VDIFF+1V”, the ISL6308 will restart at the beginning
of soft-start.
Overcurrent Protection
The ISL6308 detects overcurrent events by comparing the
droop voltage, V DROOP , to the OCSET voltage, V OCSET , as
shown in Figure 13. The droop voltage, set by the external
current sensing circuitry, is proportional to the output current
as shown in Equation 8. A constant 100μA flows through
R OCSET , creating the OCSET voltage. When the droop
voltage exceeds the OCSET voltage, the overcurrent
protection circuitry activates. Since the droop voltage is
proportional to the output current, the overcurrent trip level,
I MAX , can be set by selecting the proper value for R OCSET ,
as shown in Equation 13.
100 μ A ? R S
overvoltage condition is present and bias is applied to the
circuit.
For designs where the output voltage is scaled with a
I MAX ? R COMP ? DCR
R OCSET = ----------------------------------------------------------
(EQ. 13)
resistor divider (as shown in Figure 6), the highest DAC
reference should normally be selected, in order to give the
most useful fixed OVP trip point during soft-start, as well as
after soft-start, where the OVP trip is referenced to the DAC.
Once an overvoltage condition ends the ISL6308 continues
normal operation and PGOOD returns high.
Pre-POR Overvoltage Protection
Prior to PVCC and VCC exceeding their POR levels, the
ISL6308 is designed to protect the load from any overvoltage
events that may occur. This is accomplished by means of an
internal 10k Ω resistor tied from PHASE to LGATE, which
turns on the lower MOSFET to control the output voltage
until the overvoltage event ceases or the input power supply
17
Once the output current exceeds the overcurrent trip level,
V DROOP will exceed V OCSET , and a comparator will trigger
the converter to begin overcurrent protection procedures. At
the beginning of overcurrent shutdown, the controller turns
off both upper and lower MOSFETs. The system remains in
this state for a period of 4096 switching cycles. If the
controller is still enabled at the end of this wait period, it will
attempt a soft-start (as shown in Figure 14). If the fault
remains, the trip-retry cycles will continue indefinitely until
either the controller is disabled or the fault is cleared. Note
that the energy delivered during trip-retry cycling is much
less than during full-load operation, so there is no thermal
hazard.
FN9208.4
September 30, 2008
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