参数资料
| 型号： | ISL8120IRZEC |
| 厂商： | Intersil |
| 文件页数： | 23/33页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM VM 32-QFN |
| 标准包装： | 60 |
| PWM 型： | 电压模式 |
| 输出数： | 2 |
| 频率 - 最大： | 1.5MHz |
| 占空比： | 90% |
| 电源电压： | 3 V ~ 22 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 32-VFQFN 裸露焊盘 |
| 包装： | 管件 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页当前第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页
ISL8120IR
VIN
FIRST PWM PULSE
SS SETTLING AT VREF + 100mV
VOUT
t SS = -------------
ISL8120IRZEC
2-PHASE
EN/FF1
EN/FF2
R UP
ISL8120IRZEC
2-PHASE
EN/FF1
EN/FF2
0.0V
-100mV
1280
F SW
EN_HYS
? N
EN_HYS
PHASE
t SS_DLY ≈ ------------
R
UP
V
= ----------------------------------------------------------
I
R DOWN
384
F SW
FIGURE 6. TYPICAL 4-PHASE WITH FAULT HANDSHAKE
While EN/FF is pulled to ground, a constant voltage (0.8V) is
fed into the ramp generator to maintain a minimum
peak-to-peak ramp.
FIGURE 7. SOFT-START WITH VOUT = 0V
Since the EN/FF pins are pulled down under fault conditions,
the pull-up resistor (R UP ) should be scaled to sink no more
than 5mA current from EN/FF pin. Essentially, the EN/FF
pins cannot be directly connected to VCC.
UV
FIRST PWM PULSE
SS SETTLING AT VREF + 100mV
VOUT
Soft-start
The ISL8120IRZEC has two independent digital pre-charged
soft-start circuitry, which has a rise time inversely
proportional to the switching frequency and is determined by
an digital counter that increments with every pulse of the
-100mV
FIGURE 8. SOFT-START WITH VOUT = UV
phase clock. Refer to Figure 7. The full soft-start time from
0V to 0.6V can be estimated by Equation 1.
FIRST PWM PULSE
OV = 113%
t SS = -------------
1280
f SW
The ISL8120IRZEC has the ability to work under a
(EQ. 1)
VOUT TARGET VOLTAGE
pre-charged output (see Figure 8). The output voltage would
not be yanked down during pre-charged start-up. If the pre-
charged output voltage is greater than the final target level
but prior to 113% setpoint, the switching will not start until the
output voltage reduces to the target voltage and the first
PWM pulse is generated (see Figure 9). The maximum
FIGURE 9. SOFT-START WITH VOUT BELOW OV BUT
ABOVE FINAL TARGET VOLTAGE
Power-Good
CHANNEL 1 UV/OV
allowable pre-charged level is 113%. If the pre-charged level
is above 113% but below 120%, the output will hiccup
between 113% (LGATE turns on) and 87% (LGATE turns off)
while EN/FF is pulled low. If the pre-charged load voltage is
above 120% of the targeted output voltage, then the
controller will be latched off and not be able to power-up.
CHANNEL 2 UV/OV
END OF SS1
END OF SS2
OR
AND
VMON1, 2
PGOOD
+20%
< +20%
+13%
+9%
V REF
For above target pre-charged start-up, the output voltage
would not change until the end of the soft-start. If the initial
dip is below the UV level, the LGATE could be turned off. In
such an event, the body-diode drop of the low-side FET will
be sensed and could potentiality cause an OCP event for
-9%
-13%
r DS(ON) current sensing applications.
UV
GOOD
PRE-OV (NO LATCH)
GOOD
UV
FIGURE 10. POWER-GOOD THRESHOLD WINDOW
23
FN6763.2
November 11, 2011
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