参数资料
型号: ISL8120IRZEC
厂商: Intersil
文件页数: 28/33页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM VM 32-QFN
标准包装: 60
PWM 型: 电压模式
输出数: 2
频率 - 最大: 1.5MHz
占空比: 90%
电源电压: 3 V ~ 22 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 85°C
封装/外壳: 32-VFQFN 裸露焊盘
包装: 管件
ISL8120IR
The reason of which is practical especially for low DCR
applications the PCB and inductor pad soldering resistance
would have large effects in total impedance affecting the
DCR voltage to be sensed.
1μF
2 Ω
2.65V TO 5.6V
10μF
3V TO 26.4V
When OCP is triggered, the controller pulls EN/FF low
immediately to turn off UGATE and LGATE. However, if the
VCC
PVCC
VIN
output overshoot is greater than 113% at EN/FF = LOW,
LGATE turns ON until the output voltage drops below 87%.
A delay time, equal to 3 soft-start intervals, is entered to
allow the disturbance to clear. After the delay time, the
controller then initiates a soft-start interval. If the output
voltage comes up and returns to the regulation, PGOOD
transitions high. If the OC trip is exceeded during the
soft-start interval, the controller pulls EN/VFF low again. The
PGOOD signal will remain low and the soft-start interval will
be allowed to expire. Another soft-start interval will be
initiated after the delay interval. If an overcurrent trip occurs
again, this same cycle repeats until the fault is removed.
There is a100ns delay to prevent any fault triggering during
start-up or load transient. For a hard short of the output, the
overcurrent protection reduces the regulator RMS output
current much less than 60% of the full load current by putting
the controller into hiccup mode.
Internal Series Linear and Power Dissipation
Z1
Z2
5V
FIGURE 16. INTERNAL REGULATOR IMPLEMENTATION
The LDO is capable to supply 250mA with regulated 5.4V
output. In 3.3V input applications, when the VIN pin voltage
is 3V, the LDO still can supply 150mA while maintaining LDO
output voltage higher than VCC falling threshold to keep IC
operating. Figure 17 shows the LDO voltage drop under
different load current. However, its thermal capability should
not be exceeded. The power dissipation inside the IC could
be estimated with Equation 7.
6.0
5.5
The VIN pin is connected to PVCC with an internal series
linear regulator (1W Typical), which is internally
compensated. The PVCC and VIN pins should have the
recommended bypasses connected to GND for proper
operation. The internal series linear regulator ’s input (VIN)
can range between 3V to 22V. The internal linear regulator is
to provide power for both the internal MOSFET drivers
through the PVCC pin and the analog circuitry through the
5.0
4.5
4.0
3.5
3.0
2.5
2.0
PVCC @ 250mA + Iq
PVCC @ 100mA + Iq
PVCC @ 140mA + Iq
Iq IS AROUND 15mA
VCC pin. The VCC pin should be connected to the PVCC pin
with an RC filter to prevent high frequency driver switching
2.5
3.0
3.5
4.0 4.5 5.0 5.5
VIN PIN VOLTAGE (V)
6.0
6.5
7.0
noise from entering the analog circuitry. When VIN drops
below 5.0V, the pass element will saturate; PVCC will track
FIGURE 17. PVCC vs VIN VOLTAGE
VIN, minus the dropout of the linear regulator. When used
with an external 5V supply, VIN pin is recommended to be
P IC = ( VIN – PVCC ) ? I VIN + P DR
(EQ. 7)
I VIN = ? ? ? PVCC ? F SW + I Q_VIN
? Q G1 ? N Q1 Q G2 ? N Q2 ?
tied directly to PVCC.
------------------------------ + ------------------------------
? V GS1 V GS2 ?
28
FN6763.2
November 11, 2011
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