参数资料
型号: ISL8120IRZEC
厂商: Intersil
文件页数: 31/33页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM VM 32-QFN
标准包装: 60
PWM 型: 电压模式
输出数: 2
频率 - 最大: 1.5MHz
占空比: 90%
电源电压: 3 V ~ 22 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 85°C
封装/外壳: 32-VFQFN 裸露焊盘
包装: 管件
ISL8120IR
loading, Channel 1 might drop faster than Channel 2. To solve
this race condition, Channel 2 can either power up from
Channel 1 or bridge the Channel 1 with a high current
Schottky diode. If the system requires to shutdown both
channels when either has a fault, tying EN/FF1 and EN/FF2
will do the job. In DDR mode, Channel 1 delays 60° over
Channel 2.
V OS_DA should set to zero when the differential amplifier is
in the loop, the differential amplifier ’s input impedance
(R DIF ) is typically 500k Ω with a tolerance of 20% (R DIF %)
and can be neglected when R OS is less than 100 Ω . To set a
precision setpoint, R OS can be scaled by two paralleled
resistors.
In Dual mode, depending upon the resistor divider level of
VCC
VSEN2-
REFIN from VCC, the ISL8120IRZEC operates as a dual
VDDQ
PHASE-SHIFTED
CLOCK
PWM controller for two independent regulators with a phase
shift as shown in Table 2. The phase shift is latched as VCC
raises above POR and cannot be changed on-the-fly.
k*R
CLKOUT/REFIN
ISL8120IRZEC
STATE
MACHINE
TABLE 2.
MODE
DECODING
REFIN RANGE
PHASE for CHANNEL
2 WRT CHANNEL 1
REQUIRED
REFIN
R
700mV
k = ------------------ – 1
DDR
Dual
<29% of VCC
29% to 45% of
VCC
-60°
0.6V
37% VCC
VDDQ
0.6V
INTERNAL SS
0.6V
Dual
45% to 62% of
90°
53% VCC
FB2
E/A2
VCC
Dual
62% to VCC
180°
VCC
FIGURE 23. SIMPLIFIED DDR IMPLEMENTAION
Internal Reference and System Accuracy
The internal reference is set to 0.6V. Including bandgap
variation and offset of differential and error amplifiers, it has
an accuracy of 0.9% over industrial temperature range.
While the remote sense is not used, its offset (V OS_DA )
should be included in the tolerance calculation. Equations 9
and 10 show the worst case of system accuracy calculation.
VSENSE- (REMOTE)
VOUT (LOCAL)
10 Ω
VSENSE+ (REMOTE)
GND (LOCAL)
10 Ω
C SEN
R OS
R FB
Z FB
Z COMP
VCC
VSEN-
VSEN+
VMON
FB
COMP
PGOOD
700mV
GAIN=1
V REF
OV/UV
COMP
ERROR AMP
PGOOD
FIGURE 24. SIMPLIFIED REMOTE SENSING IMPLEMENTATION
31
FN6763.2
November 11, 2011
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