Functional Description and Application Information
Interrupt Module (S12SINTV1)
MM912F634
Freescale Semiconductor
193
2.
Clock monitor reset request
3.
COP watchdog reset request
4.29.4.4
Exception Priority
The priority (from highest to lowest) and address of all exception vectors issued by the 9S12I32PIMV1 module upon request by
4.29.5
Initialization/Application Information
4.29.5.1
Initialization
After system reset, software should:
1.
Initialize the interrupt vector base register if the interrupt vector table is not located at the default location
(0xFF80–0xFFF9).
2.
Enable I bit maskable interrupts by clearing the I bit in the CCR.
3.
Enable the X bit maskable interrupt by clearing the X bit in the CCR.
4.29.5.2
Interrupt Nesting
The interrupt request scheme makes it possible to nest I bit maskable interrupt requests handled by the CPU.
I bit maskable interrupt requests can be interrupted by an interrupt request with a higher priority.
I bit maskable interrupt requests cannot be interrupted by other I bit maskable interrupt requests, per default. In order to make
an interrupt service routine (ISR) interruptible, the ISR must explicitly clear the I bit in the CCR (CLI). After clearing the I bit, other
I bit maskable interrupt requests can interrupt the current ISR.
An ISR of an interruptible I bit maskable interrupt request could basically look like this:
1.
Service interrupt, e.g., clear interrupt flags, copy data, etc.
2.
Clear I bit in the CCR by executing the instruction CLI (thus allowing other I bit maskable interrupt requests)
3.
Process data
4.
Return from interrupt by executing the instruction RTI
Table 249. Exception Vector Map and Priority
Source
0xFFFE
Pin reset, power-on reset, illegal address reset
0xFFFC
Clock monitor reset
0xFFFA
COP watchdog reset
(Vector base + 0x00F8)
Unimplemented opcode trap
(Vector base + 0x00F6)
Software interrupt instruction (SWI) or BDM vector request
(Vector base + 0x00F4)
X bit maskable interrupt request (D2DI error interrupt)
(Vector base + 0x00F2)
D2DI interrupt request
(Vector base + 0x00F0–0x0082)
Device specific I bit maskable interrupt sources (priority determined by the low byte of the vector address,
in descending order)
(Vector base + 0x0080)
Spurious interrupt
Note:
174. 16 bits vector address based