Functional Description and Application Information
Serial Peripheral Interface (S12SPIV4)
MM912F634
Freescale Semiconductor
328
Figure 104. SPI Clock Format 1 (CPHA = 1)
The SS line can remain active low between successive transfers (can be tied low at all times). This format is sometimes preferred
in systems having a single fixed master and a single slave that drive the MISO data line.
Back-to-back transfers in master mode
In master mode, if a transmission has completed and a new data byte is available in the SPI data register, this byte is
sent out immediately without a trailing and minimum idle time.
The SPI interrupt request flag (SPIF) is common to both the master and slave modes. SPIF gets set one half SCK cycle after the
last SCK edge.
4.38.4.4
SPI Baud Rate Generation
NOTE
Baud rate generation consists of a series of divider stages. Six bits in the SPI baud rate register (SPPR2, SPPR1, SPPR0, SPR2,
SPR1, and SPR0) determine the divisor to the SPI module clock which results in the SPI baud rate.
The SPI clock rate is determined by the product of the value in the baud rate preselection bits (SPPR2–SPPR0) and the value
in the baud rate selection bits (SPR2–SPR0). The module clock divisor equation is shown in
Equation 4.BaudRateDivisor = (SPPR + 1)
2(SPR + 1)
Eqn. 4
When all bits are clear (the default condition), the SPI module clock is divided by 2. When the selection bits (SPR2–SPR0) are
001 and the preselection bits (SPPR2–SPPR0) are 000, the module clock divisor becomes 4. When the selection bits are 010,
the module clock divisor becomes 8, etc.
tL
tT
for tT, tl, tL
Minimum 1/2 SCK
tI
tL
Ifn
e
xt
tra
n
sf
er
b
egi
ns
he
re
Begin
End
SCK (CPOL = 0)
SAMPLE I
CHANGE O
SEL SS (O)
Transfer
SCK (CPOL = 1)
MSB first (LSBFE = 0):
LSB first (LSBFE = 1):
MSB
LSB
MSB
Bit 5
Bit 2
Bit 6
Bit 1
Bit 4
Bit 3
Bit 4
Bit 2
Bit 5
Bit 1
Bit 6
CHANGE O
SEL SS (I)
MOSI pin
MISO pin
Master only
MOSI/MISO
tL = Minimum leading time before the first SCK edge, not required for back-to-back transfers
tT = Minimum trailing time after the last SCK edge
tI = Minimum idling time between transfers (minimum SS high time), not required for back-to-back transfers
1
2
34
56
78
9 10
11
12
13 14
15
16
SCK Edge Number
End of Idle State
Begin of Idle State