
Functional Description and Application Information
Port Integration Module (9S12I32PIMV1)
MM912F634
Freescale Semiconductor
170
4.27.3.5
Port C Data Register (PTC)
4.27.3.6
Port D Data Register (PTD)
Table 223. Port C Data Register (PTC)
Address 0x0004
Access: User read/write
(161)76
543
210
R
0
00
0
PTC1
PTC0
W
D2DI
Function
——
———
—
D2DINT
D2DCLK
Reset
0
000
00
Note:
161. Read: Anytime.
Write: Anytime.
Table 224. PTC Register Field Descriptions
Field
Description
1
PTC
Port C general purpose input/output data—Data Register
Port C pin 1 is associated with the D2DINT signal of the D2DI module.
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the buffered and
synchronized pin input state is read.
0
PTC
Port C general purpose input/output data—Data Register
Port C pin 0 is associated with the D2DCLK signal of the D2DI module.
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the buffered and
synchronized pin input state is read.
Table 225. Port D Data Register (PTD)
Address 0x0005
Access: User read/write
(162)76
543
210
R
PTD7
PTD6
PTD5
PTD4
PTD3
PTD2
PTD1
PTD0
W
D2DI
Function
D2DDAT7
D2DDAT6
D2DDAT5
D2DDAT4
D2DDAT3
D2DDAT2
D2DDAT1
D2DDAT0
Reset
0
000
00
Note:
162. Read: Anytime.
Write: Anytime.
Table 226. PTD Register Field Descriptions
Field
Description
7-0
PTD
Port D general purpose input/output data—Data Register
Port D pins 7 through 0 are associated with the D2DI data signals of the D2DI module if enabled in 8-bit mode.
Port D pins 3 through 0 are associated with the D2DI data signals of the D2DI module if enabled in 4-bit mode.
When not used with the alternative function, these pins can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the buffered and
synchronized pin input state is read.