Functional Description and Application Information
Background Debug Module (S12SBDMV1)
MM912F634
Freescale Semiconductor
207
Figure 64 shows the host receiving a logic 0 from the target. Since the host is asynchronous to the target, there is up to a one
clock-cycle delay from the host-generated falling edge on BKGD to the start of the bit time as perceived by the target. The host
initiates the bit time but the target finishes it. Since the target wants the host to receive a logic 0, it drives the BKGD pin low for
13 target clock cycles then briefly drives it high to speed up the rising edge. The host samples the bit level about 10 target clock
cycles after starting the bit time.
Figure 64. BDM Target-to-Host Serial Bit Timing (Logic 0)
4.30.4.7
Serial Interface Hardware Handshake Protocol
NOTE
If the ACK pulse was issued by the target, the host assumes the previous command was
executed. If the CPU enters wait or stop prior to executing a hardware command, the ACK
pulse will not be issued meaning that the BDM command was not executed. After entering
wait or stop mode, the BDM command is no longer pending.
BDM commands that require CPU execution are ultimately treated at the MCU bus rate. Since the BDM clock source can be
modified relative to the bus clock, when modifying DCO clock or the bus clock divider, it is very helpful to provide a handshake
protocol in which the host could determine when an issued command is executed by the CPU. The alternative is to always wait
the amount of time equal to the appropriate number of cycles at the slowest possible rate the clock could be running. This
sub-section will describe the hardware handshake protocol.
The hardware handshake protocol signals to the host controller when an issued command was successfully executed by the
target. This protocol is implemented by a 16 serial clock cycle low pulse followed by a brief speedup pulse in the BKGD pin. This
pulse is generated by the target MCU when a command, issued by the host, has been successfully executed (see
Figure 65).This pulse is referred to as the ACK pulse. After the ACK pulse has finished: the host can start the bit retrieval if the last issued
command was a read command, or start a new command if the last command was a write command or a control command
(BACKGROUND, GO, GO_UNTIL(169) or TRACE1). The ACK pulse is not issued earlier than 32 serial clock cycles after the BDM
command was issued. The end of the BDM command is assumed to be the 16th tick of the last bit. This minimum delay assures
enough time for the host to perceive the ACK pulse. Note also that, there is no upper limit for the delay between the command
and the related ACK pulse, since the command execution depends upon the CPU bus, which in some cases could be very slow
due to long accesses taking place.This protocol allows a great flexibility for the POD designers, since it does not rely on any
accurate time measurement or short response time to any event in the serial communication.
Earliest
Start of
Next Bit
BDM Clock
(Target MCU)
Host
Drive to
BKGD Pin
Perceived
Start of Bit Time
10 Cycles
Host Samples
BKGD Pin
Target System
Drive and
Speedup Pulse
High-impedance