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| 型号： | KSZ8864RMN-EVAL |
| 厂商： | Micrel Inc |
| 文件页数： | 37/111页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR KSZ8864RMN |
| 标准包装： | 1 |
| 主要目的： | 接口，以太网控制器（PHY 和 MAC） |
| 嵌入式： | 否 |
| 已用 IC / 零件： | KSZ8864RMN |
| 已供物品： | 板 |
| 相关产品： | 576-3787-ND - IC ETHERNET SW 4PORT 64QFN |
| 其它名称： | 576-3869 |
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1997 Microchip Technology Inc.
DS30444E - page 31
PIC16C9XX
5.0
PORTS
Some pins for these ports are multiplexed with an alter-
nate function for the peripheral features on the device.
In general, when a peripheral is enabled, that pin may
not be used as a general purpose I/O pin.
5.1
PORTA and TRISA Register
The RA4/T0CKI pin is a Schmitt Trigger input and an
open drain output. All other RA port pins have TTL input
levels and full CMOS output drivers. All RA pins have
data direction bits (TRISA register) which can congure
these pins as output or input.
Setting a bit in the TRISA register puts the correspond-
ing output driver in a hi-impedance mode. Clearing a bit
in the TRISA register puts the contents of the output
latch on the selected pin.
Reading the PORTA register reads the status of the
pins whereas writing to it will write to the port latch. All
write operations are read-modify-write operations.
Therefore, a write to a port implies that the port pins are
read, this value is modied, and then written to the port
data latch.
Pin RA4 is multiplexed with the Timer0 module clock
input to become the RA4/T0CKI pin.
For the PIC16C924 only, other PORTA pins are multi-
plexed with analog inputs and the analog VREF input.
The operation of each pin is selected by clearing/set-
ting the control bits in the ADCON1 register (A/D Con-
trol Register1).
The TRISA register controls the direction of the RA
pins, even when they are being used as analog inputs.
The user must ensure the bits in the TRISA register are
maintained set when using them as analog inputs.
EXAMPLE 5-1:
INITIALIZING PORTA
BCF
STATUS, RP0
; Select Bank0
BCF
STATUS, RP1
CLRF
PORTA
; Initialize PORTA
BSF
STATUS, RP0
;
MOVLW
0xCF
; Value used to
; initialize data
; direction
MOVWF
TRISA
; Set RA<3:0> as inputs
; RA<5:4> as outputs
; RA<7:6> are always
; read as '0'.
Note:
On a Power-on Reset, these pins are con-
gured as analog inputs and read as '0'.
FIGURE 5-1:
BLOCK DIAGRAM OF PINS
RA3:RA0 AND RA5
FIGURE 5-2:
BLOCK DIAGRAM OF
RA4/T0CKI PIN
Data
bus
Q
D
Q
CK
Q
D
Q
CK
Q
D
EN
P
N
WR
Port
WR
TRIS
Data Latch
TRIS Latch
RD TRIS
RD PORT
VSS
VDD
I/O pin(1)
Note 1: I/O pins have protection diodes to VDD and VSS.
Analog
input
mode
TTL
input
buffer
To A/D Converter (PIC16C924 only)
Data
bus
WR
PORT
WR
TRIS
RD PORT
Data Latch
TRIS Latch
RD TRIS
Schmitt
Trigger
input
buffer
N
VSS
I/O pin(1)
TMR0 clock input
Note 1: I/O pin has protection diodes to VSS only.
Q
D
Q
CK
Q
D
Q
CK
EN
Q
D
EN
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