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| 型号： | KSZ8864RMN-EVAL |
| 厂商： | Micrel Inc |
| 文件页数： | 81/111页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR KSZ8864RMN |
| 标准包装： | 1 |
| 主要目的： | 接口，以太网控制器（PHY 和 MAC） |
| 嵌入式： | 否 |
| 已用 IC / 零件： | KSZ8864RMN |
| 已供物品： | 板 |
| 相关产品： | 576-3787-ND - IC ETHERNET SW 4PORT 64QFN |
| 其它名称： | 576-3869 |
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1997 Microchip Technology Inc.
DS30444E - page 71
PIC16C9XX
Figure 11-13 and Figure 11-14 show Master-transmit-
ter and Master-receiver data transfer sequences.
When a master does not wish to relinquish the bus (by
generating a STOP condition), a repeated START con-
dition (Sr) must be generated. This condition is identical
to the start condition (SDA goes high-to-low while SCL
is high), but occurs after a data transfer acknowledge
pulse (not the bus-free state). This allows a master to
send “commands” to the slave and then receive the
requested information or to address a different slave
device. This sequence is shown in Figure 11-15.
FIGURE 11-13: MASTER-TRANSMITTER SEQUENCE
FIGURE 11-14: MASTER-RECEIVER SEQUENCE
FIGURE 11-15: COMBINED FORMAT
For 7-bit address:
S
Slave Address
First 7 bits
S
R/W A1 Slave Address
Second byte
A2
Data A
Data
P
A master transmitter addresses a slave receiver
with a 10-bit address.
A/A
Slave Address R/W A Data A Data A/A P
'0' (write)
data transferred
(n bytes - acknowledge)
A master transmitter addresses a slave receiver with a
7-bit address. The transfer direction is not changed.
From master to slave
From slave to master
A = acknowledge (SDA low)
A = not acknowledge (SDA high)
S = Start Condition
P = Stop Condition
(write)
For 10-bit address:
For 7-bit address:
S
Slave Address
First 7 bits
S
R/W A1 Slave Address
Second byte
A2
A master transmitter addresses a slave receiver
with a 10-bit address.
Slave Address R/W A Data A Data A
P
'1' (read)
data transferred
(n bytes - acknowledge)
A master reads a slave immediately after the rst byte.
From master to slave
From slave to master
A = acknowledge (SDA low)
A = not acknowledge (SDA high)
S = Start Condition
P = Stop Condition
(write)
For 10-bit address:
Slave Address
First 7 bits
Sr
R/W A3
A
Data A
P
Data
(read)
Combined format:
S
Combined format - A master addresses a slave with a 10-bit address, then transmits
Slave Address R/W A Data A/A Sr
P
(read)
Sr = repeated
Transfer direction of data and acknowledgment bits depends on R/W bits.
From master to slave
From slave to master
A = acknowledge (SDA low)
A = not acknowledge (SDA high)
S = Start Condition
P = Stop Condition
Slave Address
First 7 bits
Sr
R/W A
(write)
data to this slave and reads data from this slave.
Slave Address
Second byte
Data
Sr Slave Address
First 7 bits
R/W A Data A
A P
A
Data A/A
Data
(read)
Slave Address R/W A Data A/A
Start Condition
(write)
Direction of transfer
may change at this point
(read or write)
(n bytes + acknowledge)
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