参数资料
型号: LTC1735CGN-1#TRPBF
厂商: Linear Technology
文件页数: 10/28页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM CM 16-SSOP
标准包装: 2,500
PWM 型: 电流模式
输出数: 1
频率 - 最大: 335kHz
占空比: 99.4%
电源电压: 3.5 V ~ 30 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: 0°C ~ 85°C
封装/外壳: 16-SSOP(0.154",3.90mm 宽)
包装: 带卷 (TR)
LTC1735-1
OPERATIO
POWER GOOD
(Refer to Functional Diagram)
over the widest possible output current range. This con-
A window comparator monitors the output voltage and its
open-drain output is pulled low when the divided down
output voltage (appearing at the V OSENSE pin) is not within
± 7.5% of the reference voltage of 0.8V.
During a programmed output voltage transition (i.e., a
transition from 1.55V to 1.3V) the PGOOD open-drain
output will be pulled low and Burst Mode operation will be
disabled until the output voltage is within 7.5% of its newly
programmed value.
When the PGOOD pin is driven by an external oscillator
through a series resistor, cycle-skipping operation is
invoked and the internal oscillator is synchronized to the
external clock by comparator C. In this mode, the 25%
minimum inductor current clamp is removed, providing
low noise, constant frequency discontinuous operation
APPLICATIO S I FOR ATIO
The basic LTC1735-1 application circuit is shown in
Figure 1 on the first page of this data sheet. External
component selection is driven by the load requirement
stant frequency operation is not quite as efficient as Burst
Mode operation, but does provide a lower noise, constant
frequency operation. When the power good window com-
parator indicates the output is not in regulation, the
PGOOD pin is pulled to ground and synchronization is
inhibited. Obviously when driving the PGOOD pin with an
external clock the power good indication is not available
unless additional circuitry is added.
If the PGOOD pin is tied to ground, continuous operation
is forced. This operation is the least efficient mode, but is
desirable in certain applications. The output can source
or sink current in this mode. When forcing continuous
operation and sinking current, current will be forced back
into the main power supply potentially boosting the input
supply to dangerous voltage levels —BEWARE.
Allowing a margin for variations in the LTC1735-1 and
external component values yields:
and begins with the selection of R SENSE . Once R SENSE
is known, C OSC and L can be chosen. Next, the power
MOSFETs and D1 are selected. The operating frequency
R SENSE =
50mV
I MAX
and the inductor are chosen based largely on the desired
amount of ripple current. Finally, C IN is selected for its
ability to handle the large RMS current into the converter
and C OUT is chosen with low enough ESR to meet the
output voltage ripple and transient specifications. The
circuit shown in Figure 1 can be configured for operation
up to an input voltage of 28V (limited by the external
MOSFETs).
R SENSE Selection For Output Current
R SENSE is chosen based on the required output current.
The LTC1735-1 current comparator has a maximum
threshold of 75mV/R SENSE and an input common mode
range of SGND to 1.1(INTV CC ). The current comparator
threshold sets the peak of the inductor current, yielding a
maximum average output current I MAX equal to the peak
value less half the peak-to-peak ripple current, ? I L .
10
C OSC Selection for Operating Frequency
and Synchronization
The choice of operating frequency and inductor value is
a trade-off between efficiency and component size. Low
frequency operation improves efficiency by reducing
MOSFET switching losses, both gate charge loss and
transition loss. However, lower frequency operation
requires more inductance for a given amount of ripple
current.
The LTC1735-1 uses a constant frequency architecture
with the frequency determined by an external oscillator
capacitor C OSC . Each time the topside MOSFET turns on,
the voltage on C OSC is reset to ground. During the on-time,
C OSC is charged by a fixed current. When the voltage on the
capacitor reaches 1.19V, C OSC is reset to ground. The
process then repeats.
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