参数资料
型号: LTC1735CGN-1#TRPBF
厂商: Linear Technology
文件页数: 25/28页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM CM 16-SSOP
标准包装: 2,500
PWM 型: 电流模式
输出数: 1
频率 - 最大: 335kHz
占空比: 99.4%
电源电压: 3.5 V ~ 30 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: 0°C ~ 85°C
封装/外壳: 16-SSOP(0.154",3.90mm 宽)
包装: 带卷 (TR)
LTC1735-1
APPLICATIO S I FOR ATIO
LTC1735-1. The V OSENSE line should not be routed
close to any other nodes with high slew rates.
3. Are the SENSE + and SENSE – leads routed together with
minimum PC trace spacing? The filter capacitor be-
tween SENSE + and SENSE – should be as close as
possible to the LTC1735-1. Ensure accurate current
sensing with kelvin connections to the SENSE resistors
shown in Figure 13. Series resistance can be added to
the SENSE lines to increase noise rejection.
4. Does the (+) terminal of C IN connect to the drain of the
topside MOSFET(s) as closely as possible? This capaci-
tor provides the AC current to the MOSFET(s).
INTV CC
5. Is the INTV CC decoupling capacitor connected closely
between INTV CC and the power ground pin? This capaci-
tor carries the MOSFET driver peak currents. An addi-
tional 1 μ F ceramic placed immediately next to the INTV CC
and PGND pins can help improve noise performance.
6. Keep the switching node (SW), Top Gate node (TG), and
Boost node (BOOST) away from sensitive small-signal
nodes, especially from the voltage and current sensing
feedback pins. All of these nodes have very large and
fast moving signals and therefore should be kept on the
“output side” (Pins 9 to 16) of the LTC1735-1 and
occupy minimum PC trace area.
+
C SS
R C
C C2
C OSC 1
2
C C 3
4
5
1000pF 6
7
47pF 8
C OSC TG
RUN/SS BOOST
I TH LTC1735-1 SW
PGOOD V IN
SENSE – INTV CC
SENSE + BG
V OSENSE PGND
SGND EXTV CC
16
15
14
13
12
11
10
9
+
D B
4.7 μ F
C B
Q1
D1
C IN
Q2
V IN
L1
R1
R2
C OUT
R SENSE
V OUT
+
1735-1 F12
Figure 12. LTC1735-1 Layout Diagram
HIGH CURRENT PATH
1735-1 F13
CURRENT SENSE
RESISTOR
SENSE + SENSE –
(R SENSE )
Figure 13. Kelvin Sensing R SENSE
25
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