参数资料
型号: LTC1735CGN-1#TRPBF
厂商: Linear Technology
文件页数: 24/28页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM CM 16-SSOP
标准包装: 2,500
PWM 型: 电流模式
输出数: 1
频率 - 最大: 335kHz
占空比: 99.4%
电源电压: 3.5 V ~ 30 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: 0°C ~ 85°C
封装/外壳: 16-SSOP(0.154",3.90mm 宽)
包装: 带卷 (TR)
LTC1735-1
APPLICATIO S I FOR ATIO
P SYNC =
Design Example
As a design example, assume V IN = 12V (nominal), V IN =
22V (max), V OUT = 1.5V, I MAX = 12A and f = 300kHz,
22V – 1 .5V
22 V
= 959 mW
( 12 A ) ( 2 1 . 1 ) ( 0 . 0065 ? )
R SENSE and C OSC can immediately be calculated:
R SENSE = 50mV/12A = 0.042 ?
C OSC = 1.61(10 7 )/(300kHz) – 11pF = 43pF
Assume a 1.2 μ H inductor and check the actual value of the
ripple current. The following equation is used :
Thanks to current foldback, the bottom MOSFET dissipa-
tion in short circuit will be less than under full-load
conditions.
C IN is chosen for an RMS current rating of at least 6A at
temperature. C OUT is chosen with an ESR of 0.01 ? for low
output ripple. The output ripple in continuous mode will be
V OUT ? V OUT ?
( f )( L ) ?
V IN ?
? I L =
? 1 – ?
highest at the maximum input voltage. The output voltage
ripple due to ESR is approximately:
V ORIPPLE = R ESR ( ? I L ) = 0.01 ? (3.9A) = 39mV P-P
? I L =
? = 3 . 9 A
? 1 –
R 1 ( MAX ) = 24 k ? ? = 21 . 3 k
The  highest  value  of  the  ripple  current  occurs  at  the
maximum input and output voltages:
1 . 5 V ? 1 . 5 V ?
300 kHz ( 1 . 2 μ H ) ? 22 V ?
The maximum ripple current is 32% of maximum output
current, which is about right.
Next, verify the minimum on-time of 200ns is not violated.
The minimum on-time occurs at maximum V IN and mini-
Since the output voltage is below 2.4V, the output resistive
divider will need to be sized to not only set the output
voltage but also to absorb the SENSE pins specified input
current.
? 0 . 8 V ?
? 2 . 4 V – 1 . 5 V ?
Choosing 1% resistors: R1 = 21k and R2 = 18.7k yields an
output voltage of 1.512V.
= = = 227 ns
mum V OUT .
t ON ( MIN )
V OUT 1 . 5 V
V IN ( MAX ) f 22 V ( 300 kHz )
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
The power dissipation on the topside MOSFET can be
easily estimated. Choosing a Fairchild FDS6612A results
in; R DS(ON) = 0.03 ? , C RSS = 80pF. At maximum input
voltage with T(estimated) = 50 ° C:
LTC1735-1. These items are also illustrated graphically in
the layout diagram of Figure 12. Check the following in
your layout:
1. Are the signal and power grounds segregated? The
P MAIN =
1 .5V
22 V
( 12 ) 2 [ 1 + ( 0 . 005 )( 50 ° C – 25 ° C ) ] ( 0 . 03 ? )
LTC1735-1 PGND pin should tie to the ground plane
close to the input capacitor(s). The SGND pin should
then connect to PGND and all components that connect
+ 1 . 7 ( 22 V ) ( 12 A )( 80 pF )( 300 kHz )
2
= 568 mW
Because the duty cycle of the bottom MOSFET is much
greater than the top, two larger MOSFETs must be paral-
leled. Choosing Fairchild FDS6680A MOSFETs yields a
parallel R DS(ON) of 0.0065 ? . The total power dissipation
for both bottom MOSFETs, again assuming T = 50 ° C, is:
to SGND should make a single-point tie to the SGND
pin. The synchronous MOSFET source should connect
to the input capacitor(s) ground.
2. Does the V OSENSE pin connect directly to the feedback
resistors? The resistive divider R1, R2 must be con-
nected between the (+) plate of C OUT and signal ground.
The 47pF capacitor from V OSENSE to SGND should be
as close as possible to the LTC1735-1. Be careful
locating the feedback resistors too far away from the
24
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