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参数资料
| 型号： | LTC3838EUHF#TRPBF |
| 厂商： | Linear Technology |
| 文件页数： | 16/54页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM CM 38-QFN |
| 标准包装： | 2,500 |
| 系列： | PolyPhase® |
| PWM 型： | 电流模式 |
| 输出数： | 2 |
| 频率 - 最大： | 2MHz |
| 电源电压： | 4.5 V ~ 38 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 125°C |
| 封装/外壳： | 38-WFQFN 裸露焊盘 |
| 包装： | 带卷 (TR) |
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LTC3838
OPERATION (Refer to Functional Diagram)
If the MODE/PLLIN pin is left open or connected to signal
ground, the channel will transition into discontinuous mode
operation, where a current reversal comparator (I REV ) shuts
off the bottom MOSFET (M B ) as the inductor current ap-
proaches zero, thus preventing negative inductor current
and improving light-load efficiency. In this mode, both
switches can remain off for extended periods of time. As
the output capacitor discharges by load current and the
output voltage droops lower, EA will eventually move the
ITH voltage above the zero current level (0.8V) to initiate
another switching cycle.
Power Good and Fault Protection
Each PGOOD pin is connected to an internal open-drain
N-channel MOSFET. An external resistor or current source
can be used to pull this pin up to 6V (e.g., V OUT1,2 or DRV CC ).
Overvoltage or undervoltage comparators (OV, UV) turn on
the MOSFET and pull the PGOOD pin low when the feedback
voltage is outside the ±7.5% window of the 0.6V refer-
ence voltage. The PGOOD pin is also pulled low when the
channel’s RUN pin is below the 1.2V threshold (hysteresis
applies), or in undervoltage lockout (UVLO). Note that feed-
back voltage of Channel 1 is sensed differentially through
V OUTSENSE1+ with respect to V OUTSENSE1– , while Channel 2
is sensed through V FB2 with respect to SGND.
When the feedback voltage is within the ±7.5% window,
the open-drain NMOS is turned off and the pin is pulled
up by the external source. The PGOOD pin will indicate
power good immediately after the feedback is within the
window. But when a feedback voltage of a channel goes
out of the window, there is an internal 50μs delay before
its PGOOD is pulled low. In an overvoltage (OV) condition,
M T is turned off and M B is turned on immediately without
delay and held on until the overvoltage condition clears.
Foldback current limiting is provided if the output is below
one-half of the regulated voltage, such as being shorted to
ground. As the feedback approaches 0V, the internal clamp
voltage for the ITH pin drops from 2.4V to around 1.27V,
which reduces the inductor valley current level to about
30% of its maximum value. Foldback current limiting is
disabled at start-up.
Frequency Selection and External Clock
Synchronization
An internal oscillator (clock generator) provides phase-
interleaved internal clock signals for individual channels
to lock up to. The switching frequency and phase of each
switching channel is independently controlled by adjust-
ing the top MOSFET turn-on time (on-time) through the
one-shot timer. This is achieved by sensing the phase
relationship between a top MOSFET turn-on signal and
its internal reference clock through a phase detector, and
the time interval of the one-shot timer is adjusted on a
cycle-by-cycle basis, so that the rising edge of the top
MOSFET turn-on is always trying to synchronize to the
internal reference clock signal for the respective channel.
The frequency of the internal oscillator can be programmed
from 200kHz to 2MHz by connecting a resistor, R T , from the
RT pin to signal ground (SGND). The RT pin is regulated
to 1.2V internally.
For applications with stringent frequency or interference
requirements, an external clock source connected to the
MODE/PLLIN pin can be used to synchronize the internal
clock signals through a clock phase-locked loop (Clock
PLL). The LTC3838 operates in forced continuous mode
of operation when it is synchronized to the external clock.
The external clock frequency has to be within ±30% of the
internal oscillator frequency for successful synchroniza-
tion. The clock input levels should be no less than 2V for
“high” and no greater than 0.5V for “low”. The MODE/
PLLIN pin has an internal 600k pull-down resistor.
Multichip Operations
The PHASMD pin determines the relative phases between
the internal reference clock signals for the two channels
as well as the CLKOUT signal, as shown in Table 1. The
phases tabulated are relative to zero degree (0°) being
defined as the rising edge of the internal reference clock
signal of Channel 1. The CLKOUT signal can be used to
synchronize additional power stages in a multiphase power
supply solution feeding either a single high current output,
or separate outputs.
3838fa
16
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| LTC3838IFE#PBF | 功能描述:IC REG CTRLR BUCK PWM CM 38TSSOP RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:PolyPhase® 标准包装:4,500 系列:PowerWise® PWM 型:控制器 输出数:1 频率 - 最大:1MHz 占空比:95% 电源电压:2.8 V ~ 5.5 V 降压:是 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:无 工作温度:-40°C ~ 125°C 封装/外壳:6-WDFN 裸露焊盘 包装:带卷 (TR) 配用:LM1771EVAL-ND - BOARD EVALUATION LM1771 其它名称:LM1771SSDX |
| LTC3838IFE#TRPBF | 功能描述:IC REG CTRLR BUCK PWM CM 38TSSOP RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:PolyPhase® 标准包装:4,500 系列:PowerWise® PWM 型:控制器 输出数:1 频率 - 最大:1MHz 占空比:95% 电源电压:2.8 V ~ 5.5 V 降压:是 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:无 工作温度:-40°C ~ 125°C 封装/外壳:6-WDFN 裸露焊盘 包装:带卷 (TR) 配用:LM1771EVAL-ND - BOARD EVALUATION LM1771 其它名称:LM1771SSDX |
| LTC3838IUHF#PBF | 功能描述:IC REG CTRLR BUCK PWM CM 38-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:PolyPhase® 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:500kHz 占空比:96% 电源电压:4 V ~ 36 V 降压:无 升压:是 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:无 工作温度:-40°C ~ 125°C 封装/外壳:24-WQFN 裸露焊盘 包装:带卷 (TR) |
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