参数资料
型号: LTC3838EUHF#TRPBF
厂商: Linear Technology
文件页数: 34/54页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM CM 38-QFN
标准包装: 2,500
系列: PolyPhase®
PWM 型: 电流模式
输出数: 2
频率 - 最大: 2MHz
电源电压: 4.5 V ~ 38 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 125°C
封装/外壳: 38-WFQFN 裸露焊盘
包装: 带卷 (TR)
LTC3838
APPLICATIONS INFORMATION
If the maximum duty cycle is reached, due to a drooping
input voltage for example, the output will drop out of
regulation. The minimum input voltage to avoid dropout is:
If the output falls by more than 50%, the maximum sense
voltage is progressively lowered, to about one-fourth of
its full value as the feedback voltage reaches 0V.
V IN(MIN) =
V OUT
D MAX
A feedback voltage exceeding 7.5% of the regulated target
of 0.6V is considered as overvoltage (OV). In such an OV
condition, the top MOSFET is immediately turned off and
At the onset of drop-out, there is a region of V IN of about
500mV that generates two discrete off-times, one being
the minimum off time and the other being an off-time that
is about 40ns to 60ns longer than the minimum off-time.
This secondary off-time is due to the extra delay in trip-
ping the internal current comparator. The two off-times
average out to the required duty cycle to keep the output
in regulation. There may be higher SW node jitter, apparent
especially when synchronized to an external clock, but the
output voltage ripple remains relatively small.
Fault Conditions: Current Limiting and Overvoltage
The maximum inductor current is inherently limited in a
current mode controller by the maximum sense voltage.
In the LTC3838, the maximum sense voltage is controlled
by the voltage on the V RNG pin. With valley current mode
control, the maximum sense voltage and the sense re-
sistance determine the maximum allowed inductor valley
current. The corresponding output current limit is:
the bottom MOSFET is turned on indefinitely until the OV
condition is removed, i.e., the feedback voltage falling
back below the 7.5% threshold by more than a hysteresis
of typical 2%. Current limiting is not active during an OV.
If the OV persists, and the BG turns on for a longer time,
the current through the inductor and the bottom MOSFET
may exceed their maximum ratings, sacrificing themselves
to protect the load.
OPTI-LOOP Compensation
OPTI-LOOP compensation, through the availability of the
ITH pin, allows the transient response to be optimized for
a wide range of loads and output capacitors. The ITH pin
not only allows optimization of the control-loop behavior
but also provides a DC-coupled and AC-filtered closed-loop
response test point. The DC step, rise time and settling
at this test point truly reflects the closed-loop response.
Assuming a predominantly 2nd order system, phase
margin and/or damping factor can be estimated using the
+ ? Δ I L
I LIMIT =
V SENSE(MAX)
R SENSE
1
2
percentage of overshoot seen at this pin.
The external series R ITH -C ITH1 filter at the ITH pin sets the
dominant pole-zero loop compensation. The values can
The current limit value should be checked to ensure that
I LIMIT(MIN) > I OUT(MAX) . The current limit value should
be greater than the inductor current required to produce
maximum output power at the worst-case efficiency.
Worst-case efficiency typically occurs at the highest V IN
and highest ambient temperature. It is important to check
for consistency between the assumed MOSFET junction
temperatures and the resulting value of I LIMIT which heats
the MOSFET switches.
To further limit current in the event of a short circuit to
ground, the LTC3838 includes foldback current limiting.
be adjusted to optimize transient response once the final
PCB layout is done and the particular output capacitor type
and value have been determined. The output capacitors
need to be selected first because their various types and
values determine the loop feedback factor gain and phase.
An additional small capacitor, C ITH2 , can be placed from
the ITH pin to SGND to attenuate high frequency noise.
Note this C ITH2 contributes an additional pole in the loop
gain therefore can affect system stability if too large. It
should be chosen so that the added pole is higher than
the loop bandwidth by a significant margin.
3838fa
34
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