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| 型号： | LTC3838EUHF#TRPBF |
| 厂商： | Linear Technology |
| 文件页数： | 24/54页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM CM 38-QFN |
| 标准包装： | 2,500 |
| 系列： | PolyPhase® |
| PWM 型： | 电流模式 |
| 输出数： | 2 |
| 频率 - 最大： | 2MHz |
| 电源电压： | 4.5 V ~ 38 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 125°C |
| 封装/外壳： | 38-WFQFN 裸露焊盘 |
| 包装： | 带卷 (TR) |
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LTC3838
APPLICATIONS INFORMATION
The maximum power loss in R1 is related to duty cycle,
and will occur in continuous mode at the maximum input
horizontal axis while the curve is approximately flat (or
the parameter Q GD if specified on a manufacturer’s data
C MILLER ?
voltage:
P LOSS
( R1 ) =
( V IN(MAX) – V OUT
R1
) ? V OUT
sheet), divided by the specified V DS test voltage:
Q GD
V DS(TEST)
Ensure that R1 has a power rating higher than this value.
If high efficiency is necessary at light loads, consider this
When the IC is operating in continuous mode, the duty
cycles for the top and bottom MOSFETs are given by:
power loss when deciding whether to use DCR sensing or
R SENSE sensing. Light load power loss can be modestly
higher with a DCR network than with a sense resistor due
D TOP =
V OUT
V IN
D BOT = 1– OUT
V IN – V OUT
? OUT
Δ V SENSE =
V IN ? f
+
? ? ?C MILLER ? V
? ? ? ?f
totheextraswitchinglossesincurredthroughR1.However,
DCR sensing eliminates a sense resistor, reduces conduc-
tion losses and provides higher efficiency at heavy loads.
Peak efficiency is about the same with either method.
To maintain a good signal-to-noise ratio for the current
sense signal, start with a ? V SENSE of 10mV. For a DCR
sensing application, the actual ripple voltage will be de-
termined by:
V
R1? C1
Power MOSFET Selection
Two external N-channel power MOSFETs must be selected
for each channel of the LTC3838 controller: one for the
top (main) switch and one for the bottom (synchronous)
switch. The gate drive levels are set by the DRV CC voltage.
This voltage is typically 5.3V. Pay close attention to the
BV DSS specification for the MOSFETs as well; most of the
logic-level MOSFETs are limited to 30V or less.
Selection criteria for the power MOSFETs include the on-
resistance, R DS(ON) , Miller capacitance, C MILLER , input
voltage and maximum output current. Miller capacitance,
C MILLER , can be approximated from the gate charge curve
usually provided on the MOSFET manufacturers’ data sheet.
C MILLER is equal to the increase in gate charge along the
V
V IN
The MOSFET power dissipations at maximum output
current are given by:
P TOP = D TOP ?I OUT(MAX)2 ?R DS(ON)(MAX) ( 1 + δ ) + V IN 2
? I OUT(MAX) ? ? R TG(UP) R TG(DOWN) ?
? 2 ? DRVCC – V MILLER V MILLER ?
P BOT = D BOT ? I OUT(MAX)2 ? R DS(ON)(MAX) ? (1 + δ )
where δ is the temperature dependency of R DS(ON) , R TG(UP)
is the TG pull-up resistance, and R TG(DOWN) is the TG pull-
down resistance. V MILLER is the Miller effect V GS voltage
and is taken graphically from the MOSFET ’s data sheet.
Both MOSFETs have I 2 R losses while the topside N-channel
equation includes an additional term for transition losses,
which are highest at high input voltages. For V IN < 20V,
the high current efficiency generally improves with larger
MOSFETs, while for V IN > 20V, the transition losses rapidly
increase to the point that the use of a higher R DS(ON) device
with lower C MILLER actually provides higher efficiency. The
synchronous MOSFET losses are greatest at high input
voltage when the top switch duty factor is low or during
short-circuit when the synchronous switch is on close to
100% of the period.
3838fa
24
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