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| 型号： | LTC3838EUHF#TRPBF |
| 厂商： | Linear Technology |
| 文件页数： | 32/54页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM CM 38-QFN |
| 标准包装： | 2,500 |
| 系列： | PolyPhase® |
| PWM 型： | 电流模式 |
| 输出数： | 2 |
| 频率 - 最大： | 2MHz |
| 电源电压： | 4.5 V ~ 38 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 125°C |
| 封装/外壳： | 38-WFQFN 裸露焊盘 |
| 包装： | 带卷 (TR) |
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LTC3838
APPLICATIONS INFORMATION
I LOAD
CLOCK
INPUT
PHASE AND
FREQUENCY
LOCKED
PHASE AND
FREQUENCY
LOCK LOST
FREQUENCY
RESTORED
QUICKLY
PHASE LOCK
RESUMED
PHASE AND
FREQUENCY
LOCK LOST
FREQUENCY
RESTORED
QUICKLY
SW
V OUT
DUE TO FAST
LOAD STEP
DUE TO FAST
LOAD STEP
3838 F10
Figure 10. Phase and Frequency Locking Behavior During Transient Conditions
mode at light load and switch into continuous conduction
at the R T programmed frequency as load increases. The TG
on-time during discontinuous conduction is intentionally
slightly extended (approximately 1.2 times the continuous
conduction on-time as calculated from V IN , V OUT and f) to
create hysteresis at the load-current boundary of continu-
ous/discontinuous conduction.
If an application requires very low (approaching minimum)
on-time, the system may not be able to maintain its full
frequency synchronization range. Getting closer to mini-
mum on-time, it may even lose phase/frequency lock at no
load or light load conditions, under which the SW on-time
is effectively longer than TG on-time due to TG/BG dead
times. This is discussed further under Minimum On-Time,
Minimum Off-Time and Dropout Operation.
Minimum On-Time, Minimum Off-Time
and Dropout Operation
The minimum on-time is the smallest duration that
LTC3838’s TG (top gate) pin can be in high or “on” state.
It has dependency on the operating conditions of the
switching regulator, and is a function of voltages on the
V IN and V OUT pins, as well as the value of external resistor
R T . A minimum on-time of 30ns can be achieved when the
V OUT pin is tied to its minimum value of 0.6V while the V IN
is tied to its maximum value of 38V. For larger values of
V OUT and/or smaller values of V IN , the minimum achievable
on-time will be longer. The valley mode control architecture
allows low on-time, making the LTC3838 suitable for high
step-down ratio applications.
The effective on-time, as determined by the SW node
pulse width, can be different from this TG on-time, as it
also depends on external components, as well as loading
conditions of the switching regulator. One of the factors that
contributes to this discrepancy is the characteristics of the
power MOSFETs. For example, if the top power MOSFET’s
turn-on delay is much smaller than the turn-off delay,
the effective on-time will be longer than the TG on-time,
limiting the effective minimum on-time to a larger value.
Light-load operation, in forced continuous mode, will
further elongate the effective on-time due to the dead
times between the “on” states of TG and BG, as shown in
Figure 11. During the dead time from BG turn-off to TG
turn-on, the inductor current flows in the reverse direction,
charging the SW node high before the TG actually turns
on. The reverse current is typically small, causing a slow
rising edge. On the falling edge, after the top FET turns off
and before the bottom FET turns on, the SW node lingers
high for a longer duration due to a smaller peak inductor
current available in light load to pull the SW node low. As
a result of the sluggish SW node rising and falling edges,
the effective on-time is extended and not fully controlled
by the TG on-time. Closer to minimum on-time, this may
cause some phase jitter to appear at light load. As load
current increase, the edges become sharper, and the phase
locking behavior improves.
3838fa
32
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