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参数资料
| 型号： | LXT350PE |
| 英文描述： | PCM TRANSCEIVER|SINGLE|CEPT PCM-30/E-1|CMOS|LDCC|28PIN|PLASTIC |
| 中文描述： | 的PCM收发器|单|优税PCM-30/E-1 |的CMOS | LDCC | 28脚|塑料 |
| 文件页数： | 27/50页 |
| 文件大小： | 1197K |
| 代理商： | LXT350PE |
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T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation
—
LXT350
Datasheet
27
2.7.4.3
Driver Failure Monitor Open
(DFMO)
This function is only available in Host mode. The DFMO bit is available in the Performance Status
Register to indicate an open condition on the lines. DFMO can generate an interrupt to the host
controller. The Transition Status Register bit TDFMO indicates a transition in the status of the bit.
Writing a 1 to ICR.CDFMO will clear or mask the interrupt.
2.7.4.4
Elastic Store Overflow/Underflow
(ESOVR and ESUNF)
This function is only available in Host mode. When the bit count in the Elastic Store (ES) is within
two bits of overflowing or underflowing the ES adjusts the output clock by
1
/
8
of a bit period. The
ES provides an indication of overflow and underflow via bits TRS.ESOVR and TSR.ESUNF.
These are
“
sticky bits
”
and will stay set to 1 until the host controller reads the register. These
interrupts can be cleared or masked by writing a 1 to the bits ICR.CESO and ICR.CESU,
respectively.
2.7.4.5
Built-In Self Test
(BIST)
The BIST function in only available in Host mode. The BIST exercises the internal circuits by
providing an internal QRSS pattern, running it through the encoders and the transmit drivers then
looping it back through the receive equalizer, jitter attenuator and decoders to the QRSS pattern
detection circuitry. The BIST is initiated by setting bit CR3.SBIST = 1. If all the blocks in this data
path operate correctly, the receive pattern detector locks onto the pattern. It then pulls INT Low and
sets the following bits:
TSR.TQRSS = 1
PSR.QRSS = 1
PSR.BIST = 1
The QPD pin also indicates completion status of the test. Initiating the BIST forces QPD High.
During the test, it remains High until the test finishes successfully, at which time it goes Low. Note
that during BIST, the TPOS/TNEG inputs must remain at logic level = 0
The most reliable test will result when a separate TCLK and MCLK are applied.
相关PDF资料 |
PDF描述 |
|---|---|
| LXT361LE | Telecommunication IC |
| LXT361PE | Telecommunication IC |
| LXT362LE | PCM TRANSCEIVER|SINGLE|T-1(DS1)|CMOS|QFP|44PIN|PLASTIC |
| LXT362PE | PCM TRANSCEIVER|SINGLE|T-1(DS1)|CMOS|LDCC|28PIN|PLASTIC |
| LXT362QE | PCM TRANSCEIVER|SINGLE|T-1(DS1)|CMOS|QFP|44PIN|PLASTIC |
相关代理商/技术参数 |
参数描述 |
|---|---|
| LXT350QE | 制造商:LEVEL1 功能描述: |
| LXT351 | 制造商:INTEL 制造商全称:Intel Corporation 功能描述:T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation |
| LXT351PE | 制造商:INTEL 制造商全称:Intel Corporation 功能描述:PCM TRANSCEIVER|SINGLE|CEPT PCM-30/E-1|CMOS|LDCC|28PIN|PLASTIC |
| LXT351QE | 制造商:INTEL 制造商全称:Intel Corporation 功能描述:PCM TRANSCEIVER|SINGLE|CEPT PCM-30/E-1|CMOS|QFP|44PIN|PLASTIC |
| LXT360 | 制造商:LVL1 制造商全称:LVL1 功能描述:Integrated T1/E1 LH/SH Transceivers for DS1/DSX-1/CSU or NTU/ISDN PRI Applications |
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