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参数资料
| 型号： | M306V8FJFP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 16-BIT, FLASH, 16 MHz, MICROCONTROLLER, PQFP116 |
| 封装： | 20 X 20 MM, 0.65 MM PITCH, PLASTIC, LQFP-116 |
| 文件页数： | 29/77页 |
| 文件大小： | 2650K |
| 代理商： | M306V8FJFP |
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M306V8FJFP
Rev.1.31
Apr 18, 2005
page 33 of 363
REJ03B0082-0131
When processor mode is changed from single-chip mode to memory extension mode, the address
bus is indeterminate until any external area is accessed.
(2) Data Bus
16 lines D0 to D15 comprise the data bus.
Do not change the input level on the BYTE pin while in operation.
(3) Chip Select Signal
_____
______
The chip select (hereafter referred to as the CS) signals are output from the CSi (i = 0 to 3) pins. These
_____
pins can be chosen to function as I/O ports or as CS by using the CSi bit in the CSR register.
Figure 4.4 shows the CSR register.
______
During 1 Mbyte mode, the external area can be separated into up to 4 by the CSi signal which is output
______
from the CSi pin. During 4 Mbyte mode, CSi signal or bank number is output from the CSi pin. Refer to
______
“Memory space expansion function”. Figure 4.5 shows the example of address bus and CSi signal
output in 1 Mbyte mode.
Function
Bit symbol
Bit name
Chip select control register
Symbol
Address
After reset
CSR
000816
0116
RW
b7
b6
b5
b4
b3
b2
b1
b0
CS1
CS0
CS3
CS2
CS0 output enable bit
CS1 output enable bit
CS2 output enable bit
CS3 output enable bit
CS1W
CS0W
CS3W
CS2W
CS0 wait bit
CS1 wait bit
CS2 wait bit
CS3 wait bit
0 : Chip select output disabled
(functions as I/O port)
1 : Chip select output enabled
0 : With wait state
1 : Without wait state
RW
(Note 1, Note 2, Note 3)
Notes 1: Where the RDY signal is used in the area indicated by CSi (i = 0 to 3) or the multiplex bus is used, set
the CSiW bit to “0” (Wait state).
2: When the PM17 bit in the PM1 register is set to “1” (wait), set the CSiW bit to “1” (wait).
3: When the CSiW bit = “0” (with wait state), the number of wait states (interms of clock cycles) can be
selected using the CSEi1W to CSEi0W bits in the CSE register.
Figure 4.4. CSR Register
Bus Control
The following describes the signals needed for accessing external devices and the functionality of software
wait.
(1) Address Bus
The address bus consists of 20 lines, A0 to A19. The address bus width can be chosen to be 12, 16 or
20 bits by using the PM06 bit in the PM0 register and the PM11 bit in the PM1 register. Table 4.4
shows the PM06 and PM11 bit set values and address bus widths.
Set value(Note)
Pin function
PM11=1
P34 to P37
Address bus wide
12 bits
PM06=1
P40 to P43
PM11=0
A12 to A15
16 bits
PM06=1
P40 to P43
PM11=0
A12 to A15
20 bits
PM06=0
A16 to A19
Note 1: No values other than those shown above can be set.
Table 4.4. PM06 and PM11 Bits Set Value and Address Bus Width
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