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参数资料
| 型号： | M306V8FJFP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 16-BIT, FLASH, 16 MHz, MICROCONTROLLER, PQFP116 |
| 封装： | 20 X 20 MM, 0.65 MM PITCH, PLASTIC, LQFP-116 |
| 文件页数： | 43/77页 |
| 文件大小： | 2650K |
| 代理商： | M306V8FJFP |
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M306V8FJFP
Rev.1.31
Apr 18, 2005
page 46 of 363
REJ03B0082-0131
Figure 4.17 shows the external memory connect example in 4 Mbyte mode.
_____
_______
In this example, the CS pin of 4-Mbyte ROM is connected to the CS0 pin of microcomputer. The 4 Mbyte
_______
ROM address input AD21, AD20 and AD19 pins are connected to the CS3, CS2 and CS1 pins of micro-
computer, respectively. The address input AD18 pin is connected to the A19 pin of microcomputer. Fig-
ures 4.18 to 4.20 show the relationship of addresses between the 4-Mbyte ROM and the microcomputer
for the case of a connection example in Figure 4.17.
In microprocessor mode, or in memory expansion mode where the PM13 bit in the PM1 register is “0”,
banks are located every 512 Kbytes. Setting the OFS bit in the DBR register to “1”(offset) allows the
accessed address to be offset by 4000016, so that even the data overlapping a bank boundary can be
accessed in succession.
In memory expansion mode where the PM13 bit is “1”, each 512-Kbyte bank can be accessed in 256
Kbyte units by switching them over with the OFS bit.
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_______
Because the SRAM can be accessed on condition that the chip select signals S2 = “H” and S1 =“L”, CS0
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____
and CS2 can be connected to S2 and S1, respectively. If the SRAM does not have the input pins to accept
____
_______
“H” active and “L” active chip select signals(S1, S2), CS0 and CS2 should be decoded external to the
chip.
17
8
M306V8
D0 to D7
A0 to A16
A17
RD
WR
CS1
CS2
CS3
CS0
A19
4M
bytes
ROM
DQ0 to DQ7
AD0 to AD16
AD17
AD18
AD19
OE
CS
128K
bytes
SRAM
DQ0 to DQ7
AD0 to AD16
S2
W
OE
S1
AD20
AD21
Note: If only one chip select pin (S1 or S2) is present,
decoding by use of an external circuit is required.
(Note)
Figure 4.17. External Memory Connect Example in 4M Byte Mode
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