参数资料
型号: M306V8FJFP
元件分类: 微控制器/微处理器
英文描述: 16-BIT, FLASH, 16 MHz, MICROCONTROLLER, PQFP116
封装: 20 X 20 MM, 0.65 MM PITCH, PLASTIC, LQFP-116
文件页数: 37/77页
文件大小: 2650K
代理商: M306V8FJFP
M306V8FJFP
Rev.1.31
Apr 18, 2005
page 40 of 363
REJ03B0082-0131
Bus mode
PM1 register
PM17 bit
CSE register
CSE31W to CSE30W bit
CSE21W to CSE20W bit
CSE11W to CSE10W bit
CSE01W to CSE00W bit
Bus cycle
CSR register
CS3W bit (Note 1)
CS2W bit (Note 1)
CS1W bit (Note 1)
CS0W bit (Note 1)
Area
Software wait
Notes 1: To use the RDY signal, set this bit to “0”.
2: To access in multiplexed bus mode, set the corresponding bit of CS0W to CS3W to “0” (with wait state).
3: After reset, the PM17 bit is set to “0” (without wait state), all of the CS0W to CS3W bits are set to “0” (with wait state), and the CSE register is set to
“0016” (one wait state for CS0 to CS3). Therefore, the internal RAM and internal ROM are accessed with no wait states, and all external areas are
accessed with one wait state.
Separate bus
Multiplexed
bus (Note 2)
1
0
1
0
1
0
002
012
102
002
012
102
2 BCLK cycles
1 BCLK cycle (read)
2 BCLK cycles (write)
2 BCLK cycles (Note 3)
3 BCLK cycles
4 BCLK cycles
2 BCLK cycles
3 BCLK cycles
4 BCLK cycles
3 BCLK cycles
Internal
RAM, ROM
External
area
1 wait
No wait
1 wait
2 waits
3 waits
1 wait
2 waits
3 waits
1 wait
002
2 BCLK cycle
SFR
0
1 BCLK cycle (Note 3)
No wait
4: When the PM17 bit is set to “1” and accessing external area, set the CSiW bit (0 to 3) in the CSR register to “0” (wait).
Table 4.10. Bit and Bus Cycle Related to Software Wait
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