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| 型号： | M306V8FJFP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 16-BIT, FLASH, 16 MHz, MICROCONTROLLER, PQFP116 |
| 封装： | 20 X 20 MM, 0.65 MM PITCH, PLASTIC, LQFP-116 |
| 文件页数： | 74/77页 |
| 文件大小： | 2650K |
| 代理商： | M306V8FJFP |
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M306V8FJFP
Rev.1.31
Apr 18, 2005
page 74 of 363
REJ03B0082-0131
Figure 7.3. Interrupt Control Registers
Symbol
Address
After reset
INT0IC to INT2IC
005D16 to 005F16
XX00X0002
Bit
name
Functio
n
Bit
symbol
b7
b6
b5
b4
b3
b2
b1
b0
ILVL0
IR
POL
No functions are assigned.
When writing to these bits, write “0”. The values in these bits
when read are indeterminate.
Interrupt priority level
select bit
Interrupt request bit
Polarity select bit
Reserved bit
0: Interrupt not requested
1: Interrupt requested
0 : Selects falling edge (Notes 3, 5)
1 : Selects rising edge
Must always be set to “0”
ILVL1
ILVL2
Note 1: This bit can only be reset by writing “0” (Do not write “1”).
Note 2: To rewrite the interrupt control register, do so at a point that does not generate the interrupt request for that
register. For details, see the “Notes of interruption” of the Usage Notes Reference Book.
Note 3: If the IFSR register’s IFSRi bit (i = 0 to 2) is “1” (both edges), set the INTiIC register’s POL bit to “0” (falling edge).
(Note 1)
Interrupt control register (Note 2)
b7
b6
b5
b4
b3
b2
b1
b0
Bit
name
Functio
n
Bit symbol
RW
Symbol
Address
After reset
TB5IC
004516
XXXXX0002
TB4IC
004616
XXXXX0002
TB3IC
004716
XXXXX0002
BCNIC
004A16
XXXXX0002
DM0IC, DM1IC
004B16, 004C16
XXXXX0002
KUPIC
004D16
XXXXX0002
ADIC
004E16
XXXXX0002
S0TIC to S2TIC
005116, 005316, 004F16
XXXXX0002
S0RIC to S2RIC
005216, 005416, 005016
XXXXX0002
TA0IC to TA4IC
005516 to 005916
XXXXX0002
TB0IC to TB2IC
005A16 to 005C16
XXXXX0002
ILVL0
I
R
Interrupt priority level
select bit
Interrupt request bit
0 : Interrupt not requested
1 : Interrupt requested
ILVL1
ILVL2
No functions are assigned.
When writing to these bits, write “0”. The values in these bits
when read are indeterminate.
(Note 1)
Note 1: IR bit write “0” only (Do not write “1”).
Note 2: To rewrite the interrupt control registers, do so at a point that does not generate the interrupt request for that
register. For details, see the “Notes of interruption” of the Usage Notes Reference Book.
0 0 0 : Level 0 (interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
b2 b1 b0
0 0 0 : Level 0 (interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
b2 b1 b0
0
RW
(b7-b4)
RW
(b7-b6)
(b5)
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