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REVISION HISTORY
38D5 Group Data Sheet
2.04
Feb 02, 2007
81
th (SCLK2-RXD)
→ th (SCLK2-SIN2)
Table 23
Limits of twH (SCLK2), twL (SCLK2): tc (SCLK1)/2–30
→ tc (SCLK2)/2–30
3.01
Aug 08, 2007
38D5 Group (Flash Memory Version For Development) Datasheet (No.
REJ03B0197) is merged.
1
Flash memory version contents: added
DESCRIPTION: Description added
Memory size (QzROM version): 640 bytes
→ 1536 bytes
Power dissipation (Flash memory version): revised
2
Fig. 1: Flash memory version: “M38D59FFFP” added, Notes: added
3
Fig. 2: Flash memory version: “M38D59FFHP” added, Notes: added
4
Table 1: Flash memory version contents: added and separates to Table 2 (Next
page)
Memory size (QzROM version); 640 bytes
→ 1536 bytes
I/O port; 32 pins
→ 36 pins
7
Table 3: I/O port P3, I/O port P4: revised
8
Table 4: OSCSEL
→ CNVSS/function: revised
9
Fig.4 “Memory type”: Flash memory version added
10
Memory Type: deleted
Memory size (QzROM version): 640 bytes
→ 1536 bytes
Fig. 5: Under development products
→ mass-produced
Table 5: Flash memory version products added
11
Table 6, Notes on Differences between QzROM and Flash Memory Versions: added
12
Central Processing Unit: revised
15
Fig. 8: Flash memory version contents: added
Notes: revised
16
Fig. 9: Flash memory version contents: added
Low/XIN mode?
→ Low-speed/XIN mode?
17
Memory: Flash memory version contents: added
ROM is revised
ROM code Protect Address in QzROM version is revised
Fig. 10: revised
18
Fig. 11: revised
19
Fig. 13: Do not write “1”
→ Not used (do not write “1”)
23
Fig. 16 (14) Port P60: Revised port Xc switch bit input to low-active
27 to 31
INTERRUPTS: revised
28
Interrupt Source Selection: interrupt source selection register → interrupt edge
selection register
External Interrupt Pin Selection: INT0, INT1 interrupt switch bit → INT0, INT1 input
port switch bit
29
Fig. 19: Do not write “1”
→ Not used (do not write “1”)
31
<Notes>: Related registers
→ Related bits, and its explain is revised
34
Fig. 25: Figure title is revised
P72 clock output control bit block is revised
35
Frequency Divided For Timer: revised
<Notes on Timer 1 to Timer 4>: (2)Writing to Timer 2, Timer 3, Timer 4
→ (2)Write
Timer 2, Timer 3, Timer4
37
Fig. 28: Figure title is revised
Timer X output 1 edge switch bit
→ Timer X output 1 active edge switch bit
Rev.
Date
Description
Page
Summary