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| 型号： | M65818AFP |
| 厂商： | Renesas Technology Corp. |
| 英文描述： | Digital Amplifier Processor of S-Master Technology |
| 中文描述： | 数字放大器处理器的S - Master技术 |
| 文件页数： | 21/39页 |
| 文件大小： | 384K |
| 代理商： | M65818AFP |
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M65818AFP
Rev.1.00, Sep.04.2003, page 21 of 38
5.11. OFLFLAG
71
OFLFLAG
pin is output the 'over flow flag' in the operation.
OFLFLAG
pin outputs "H" level by detection of over
flow from Gain Control Block and others.
The "H" level width is over 0.6msec, so detection result is held.
5.12. OUTL1+, OUTL1-, OUTL2+, OUTL2-, OUTR1+, OUTR1-, OUTR2+, OUTR2-
OUTL1+, OUTL1-, OUTL2+, OUTL2-, OUTR1+, OUTR1-, OUTR2+, and OUTR2- pins are pulse output modulated
Σ
output signal to PWM signal.
These pins are connected to external Power Driver ICs.
PWM Output Form 1, 2, 3 and 4 can be selected by serial control data(System1 mode:bit22,23 ).
PWM Output Form1 : General Modulation
PWM Output Form2 : Symmetrical Modulation
PWM Output Form3 : Modulation returned with time domain.
(The rise and fall edge of Lch and Rch in a term are reverse.)
PWM Output Form4: Modulation returned with time domain.
(The rise and fall edge of Lch and Rch in a term are same timing.)
In each 4 forms, the operating rate and bit length of PWM Output can be changed following the setting of
Σ
And the output
mute function and the output pins reverse function, can be controlled by the pin setting or serial control.
The PWM output control is shown in the following table.
Item
Output Form
Operation
Output Form Selection
1,2,3,4
Setting
Operation
Set up by the serial control system 1 mode
bit 22,23 (PWM MODE 0 and 1).
(Refer to Chapter 6.2. system 1 mode for details)
Set up by the serial control system 2 mode bit16 and bit17.
(Refer to Chapter 6.3. system 2 mode for details.)
Operating Rate and Data
Bit Length
Select to
16fso/6bit ,16fso/5bit
,32fso/5bit from operating
rate and data bit length of
Σ
.
PWM operation are
synchronized by this
setting.
Duty 50% Mute
Output Muting
Set
NSPMUTE
pin "L" or set up by serial control System 2
mode bit14 (
NSPMUTE
) "H".
(Refer to Chapter 5.13.NSPMUTE pin description and
6.3.system2 mode for details)
Set
PGMUTE
pin "L" or set up by serial control system2 mode
bit15(PGMUTE) "H".
(Refer to Chapter 5.14.
PGMUTE
pin description and 6.3
system2 mode for details)
Set up by serial control system2 mode bit9
(
CHSEL ).
Set up by serial control system1 mode bit124(PWMHP).
(Refer to Chapter 6.2. system1 mode for details.)
Absolute Zero Mute
Reverse Output
Pins Function
Reverse on Lch and Rch
of output pins.
Reverse for
OUTL1
- and
OUTR1
- of output pins.(
Output
OUTL1
+
/R1
+
data to
OUTL1
-
/OUTR1
-
data.)
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