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参数资料
| 型号： | M65818AFP |
| 厂商： | Renesas Technology Corp. |
| 英文描述： | Digital Amplifier Processor of S-Master Technology |
| 中文描述： | 数字放大器处理器的S - Master技术 |
| 文件页数： | 24/39页 |
| 文件大小： | 384K |
| 代理商： | M65818AFP |
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M65818AFP
Rev.1.00, Sep.04.2003, page 24 of 38
6. Serial Control
6.1. Gain Control Mode
No setting bits means "Don't care".
bit
1
2
3
4
5
6
7
Flag Name
MODE1
MODE2
TEST1
TEST2
NSLMT1
NSLMT2
GCONT1
Functional Explanation
Mode Setting 1
Mode Setting 2
Test Mode 1
Test Mode 2
Output Limit 1
Output Limit 1
Channel selection for Gain
Control Block 1
Channel selection for Gain
Control Block 2
H
L
"L" fixed
"L" fixed
"L" fixed
"L" fixed
INIT
L
L
L
L
L
Refer to Table 6-1-2.
L / R independence
L/R common
8
GCONT2
Lch
Rch
L
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
H
L
L
L
L
H
L
L
L
L
L
L
L
GAIN0
GAIN1
GAIN2
GAIN3
GAIN4
GAIN5
GAIN6
GAIN7
GAIN8
GAIN9
GAIN10
GAIN11
GAIN12
Gain Data Index (MSB)
Gain Data Index
Gain Data Index
Gain Data Index
Gain Data Index (LSB)
Gain Data Mantissa (MSB)
Gain Data Mantissa
Gain Data Mantissa
Gain Data Mantissa
Gain Data Mantissa
Gain Data Mantissa
Gain Data Mantissa
Gain Data Mantissa (LSB)
Output Limit (bit5,bit6:NSLMT1 ,NSLMT2 )
The M65818AFP has Over Flow Limit function which detects by input signal level and limit gain control.
Limit value is set by Gain Control Mode :bit5,bit6 ”NSLMT1, NSLMT2” and System2 Mode:bit17"NSOBIT".
The limit value setting of Gain control block and PWM output.
Table (6-1-1a). Limit Value [In the case of 6bit mode, System2 mode:bit17(NSOBIT)="L"]
DSLMT1
L
H
L
H
DSLMT2
L
L
H
H
Gain Block
±0.9375
±0.90625
±0.875
±0.84375
PWM Output (Limit Value from DS Block )
63 values (±31)
61 values (±30)
59 values (±29)
57 values (±28)
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