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| 型号： | M65818AFP |
| 厂商： | Renesas Technology Corp. |
| 英文描述： | Digital Amplifier Processor of S-Master Technology |
| 中文描述： | 数字放大器处理器的S - Master技术 |
| 文件页数： | 29/39页 |
| 文件大小： | 384K |
| 代理商： | M65818AFP |
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M65818AFP
Rev.1.00, Sep.04.2003, page 29 of 38
Table 6-2-4 Fs Selection for De-emphasis filter
(De-emphasis is "ON" except for bit9=L and bit10=L)
bit
9
10
Flag Name
EMPFS1
EMPFS2
32.0K
H
H
44.1K
L
H
48.0K
H
L
OFF
L
L
Table 6-2-5 Selection of PWM Output form
bit
22
23
Flag Name
PWMMODE0
PWMMODE1
PWM Output
Form
L
L
PWM Output
Form
H
L
PWM Output
Form
L
H
PWM Output Form
H
H
*Output Form 2 is available only under following conditions.
MCKSEL="L" (Secondary Side Master Clock 1024fso) , Serial Control System2 mode,
bit17(
NSOBIT
) = "H" (5bit), bit16(
NSSPEED
) = "L" (16fso).
In case of the setting and release for PWM Output Form 2,
Refer to "The NOTE1 at setting PWM output Form 2" on next page.
Selection of Input format (bit3,bit4:IFMT0,IFMT1)
Selection of Input format function is available only condition of `Normal` mode.
Refer to Table 6-2-1
Otherwise, Selection of Input format function is unavailable under conditions of `External 8fs Input`
and `SACD Input` modes (Interlocked with
MODE1
and
MODE2
pins).
Detail setting of `External 8fs Input` and `SACD` modes are shown in Chapter
5-4
and
5-5
.
Setting of Input Word Length (bit5,bit6:IBIT0,IBIT1).
2.
Setting of Input Data Word Length is available only MSB First Right Justified.
Refer to Table 6-2-
Selection of Input Sampling Rate (bit7,bit8:ISF0,ISF1).
3.
Refer to Table 6-2-
Fs Selection for De-emphasis Filter on/off (bit9, bit10 : EMPFS1, EMPFS2).
4.
(bit9,bit10):
("L","L")…
De-emphasis Filter is "off".
except ("L","L")… De-emphasis Filter on (Fs setting).
Refer to Table 6-2-
Zero Mute at data input (bit11: DF1IMUTE).
DF1IMUTE :
"L"…Mute release.
"H"…Mute.
The input data from
DATA
pin under normal mode is muted in this setting.
Zero Mute at Sampling Rate Converter Input (bi12: DF2IMUTE).
DF2IMUTE :
"L"…Mute release.
"H"…Mute.
DF2IMUTE is available for sampling rate converter input data.
DF2IMUTE executes zero mute of input data from
DATA
pin under condition of `Normal` mode and
from
DSDL
/
DSDR
pins under condition of `SACD-fsi ` mode.
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