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| 型号： | M65818AFP |
| 厂商： | Renesas Technology Corp. |
| 英文描述： | Digital Amplifier Processor of S-Master Technology |
| 中文描述： | 数字放大器处理器的S - Master技术 |
| 文件页数： | 23/39页 |
| 文件大小： | 384K |
| 代理商： | M65818AFP |
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M65818AFP
Rev.1.00, Sep.04.2003, page 23 of 38
(5)
BFVdd, BFVss
These pins are Power supply and GND for input/output buffer (3.3V/5V ). In a case that
BFVdd
pin
is applied at 5.0V, input/output voltage level of 34-67pins becomes 5.0V signal level. In another case
that
BFVdd
pin is supplied at 3.3V, input/output pins (34-67 pins) becomes 3.3V signal level.
58 68
5.18. Power sequences
System power-on sequencing
* Refer to following figure.
System power-on sequencing
* Refer to following figure.
X
X
X
X
X
Power(Vddxxx,XVdd,
XOVdd, DVdd, BFVdd)
Master clock
(XfsoIN, XfsiIN)
INIT
SCDT
SCSHIFT
SCLATCH
Over 5msec(*1)
Over 0sec(*2)
Over 2/fso(*3)
Power ON
Power OFF
*1 After a power supply and Master clock become to stable,
INIT
pin must be "L" over 5 msec.
*2 Data transfer is possible right after
INIT
release.
*3 Until
SCLATCH
is operated, a period over 2/fso ( fso=48kHz, over 42usec ) is necessary after
INIT
release.
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