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| 型号： | M65818AFP |
| 厂商： | Renesas Technology Corp. |
| 英文描述： | Digital Amplifier Processor of S-Master Technology |
| 中文描述： | 数字放大器处理器的S - Master技术 |
| 文件页数： | 32/39页 |
| 文件大小： | 384K |
| 代理商： | M65818AFP |
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M65818AFP
Rev.1.00, Sep.04.2003, page 32 of 38
Table 6-3-1 Setting of Down Sampling Filter Coefficient
bit
4
5
Flag Name
DSDFCO0
DSDFCO1
ROM1
L
L
ROM2
H
L
ROM3
L
H
ROM4
H
H
Table 6-3-2 DC dithering Selection at
Σ
Block
bit
19
20
Flag Name
DCDSEL0
DCDSEL1
Non-dithering
L
L
DC dithering
0.1%
H
L
DC dithering
0.2%
L
H
DC dithering0.4%
H
H
Table 6-3-3 AC dithering Selection at
Σ
Block
bit
22
23
24
Flag Name
ACDSEL0
ACDSEL1
ACDSEL2
Non-dithering
don't care
L
L
AC dithering A
L
H
L
AC dithering C
L
L
H
AC dithering E
L
H
H
Table 6-3-4 Setup Operating Rate & Bit Length of
Σ
Block
bit
16
17
pin
Flag / Pin
Name
NSSPEED
NSOBIT
MCKSEL
16fso,6bit
L
L
L(Secondary
Clock1024fso)
16fso,5bit
L
H
L(Secondary
Clock1024fso)
16fso,5bit
X
X
L(Secondary
Clock512fso)
32fso,5bit
H
H
L(Secondary
Clock1024fso)
Input Master Clock Selection (bit3:IMCKSEL).
"L":256fsi
"H":512fsi ("512fsi" are divided into half "256fsi" and operate as primary master clock.)
Selection of Down Sampling Filter Coefficient for SACD input (bi4, bit5: DSFCO 0,DSFCO 1).
Refer to Table 6-3-1.
Resynchronization (bit6: SYNC).
Resynchronization function is same at
SYNC
pin's function. Refer to Operation Explanation, Chapter 5.10.
Resynchronization process starts by
SYNC
rise edge,
therefore SYNC level must be fixed to "L" just before SYNC operation.
"Enable" of
XfsoOUT
pin Output(bit7: XfsoOEN).
"L": Clock Output (enable), "H": L fixed (disable)
Flag to "Enable" Asynchronous Detection for Secondary Block (bit8: ASYNCEN2).
ASYNCEN2 : "L"…disable.
"H"…enable.
Under condition of ASYNCEN2="L", secondary side asynchronous detection is in-effective under asynchronous
position, whether Fsol Clock is not inputted, there by M65818AFP does not operate function for instance mute
operation.
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