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| 型号： | M65818AFP |
| 厂商： | Renesas Technology Corp. |
| 英文描述： | Digital Amplifier Processor of S-Master Technology |
| 中文描述： | 数字放大器处理器的S - Master技术 |
| 文件页数： | 22/39页 |
| 文件大小： | 384K |
| 代理商： | M65818AFP |
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M65818AFP
Rev.1.00, Sep.04.2003, page 22 of 38
5.13. NSPMUTE
39
NSPMUTE
pin is input to make for PWM output to 50% duty mute.
"L": PWM output 50% duty Mute. '"H": Mute release.
5-14. PGMUTE
40
PGMUTE
pin is input to make PWM output to absolute zero mute.
"L": PWM output mute.
The case of System1 mode:bit24,PWMHP = "L"
OUTL1 (+), OUTL2 (+), OUTR1 (+), OUTR2 (+)
: "L" fixed
OUTL1 (-), OUTL2 (-), OUTR1 (-), OUTR2 (-)
: "H" fixed
The case of System1 mode:bit24,PWMHP = "H"
OUTL1 (+), OUTL2 (+), OUTR1 (+), OUTR2 (+) ,OUTL1(-),OUTR1(-)
: "L" fixed
OUTL2 (-), OUTR2 (-)
: "H" fixed
"H": MUTE release.
5.15 INIT
41
INIT is the pin for reset to all functions of M65818AFP.
"L" level : (1). Clear of data memory. (2). Initialization of Serial Control.
(3). PWM output Duty 50 %.
"L" period needs more than 5 msec.
"H" level : usual operation.
"L">"H" rise edge: Resynchronization treatment, which is same at SYNC function.
5.16. TEST1, TEST2, TEST3
TEST1,TEST2,
and
TEST3
pins are test input for factory shipping test of M65818AFP.
TEST1,TEST2,
and
TEST3
pins must be tied to "L" level on usual operation.
5.17. Power Supply and GND
Power supply and GND routes have 5 isolated lines.
(1)
VddL1+, VssL1+, VddL1-, VssL1-, VddL2+, VssL2+, VddL2-, VssL2-, VddR1+, VssR1+, VddR1-, VssR1-,
VddR2+, VssR2+, VddR2-, VssR2-, VssL, VddL, VssR, VddR
These pins are Power supply and GND for PWM output buffer block.
It has a pair of independent Power Supply, and GND to each 8 output pin. Power Supply voltage must be fixed at 5.0V.
(2)
XVdd, XVss
These pins are Power supply and GND for
XfsoIN
clock input block.
Power Supply voltage must be fixed at 5.0V.
(3)
XOVdd, XOVss
These pins are Power supply and GND for
XfsoOUT
clock output block.
Power Supply voltage must be fixed at 5.0V.
(4)
DVdd, DVss
These pins are Power supply and GND for digital block and fixed input/output
buffer only for 3.3V (32,70-74 pins). Power Supply voltage must be fixed at 3.3V
27 29 30
76 78
75 69
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