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M66592F P/W G
Rev 1.00 2004.10.01 page 2 of 125
1.2.5
Bus interfaces
The user can select either a 1.8 V or 3.3 V bus interface power supply
16-bit CPU bus interface
16-bit separate bus and 16-bit multiplex bus supported
8-bit and 16-bit DMA interface (slave function) supported
8-bit split bus (dedicated external DMA interface) supported
DMA interface has two channels built into it.
DMA transfer enables high-speed access of 40 MB/sec.
1.2.6
Pipe configuration
Internal 5 KB buffer memory for USB communication built in
Up to 8 pipes(endpoints) can be selected (including the default control pipe for endpoint 0)
Programmable pipe configuration
End point numbers can be assigned flexibly to PIPE1to PIPE7.
Transfer conditions that can be set for theeach pipe
Pipe 0: Control transfer, continuous transfer mode, 256-byte fixed single buffer
PIPE1 and PIPE2: Bulk transfer / isochronous transfer, continuous transfer mode, programmable buffer size
(up to 2 KB; double buffer can be specified)
PIPE 3 to PIPE5: Bulk transfer, continuous transfer mode, programmable buffer size (up to 2 KB; double buffer
can be specified)
PIPE6 and PIPE7: Interrupt transfer, 64-byte fixed single buffer
1.2.7
Other functions
Automatic recognition of Hi-Speed operation or Full-Speed operation based on automatic response to the reset
handshake
Byte endian swap function when using 16-bit data transfers
Transaction count function when using DMA transfers
DMA transfer termination function using external trigger (DEND pin)
Control transfer stage control function
Device state control function
Auto response function for SET_ADDRESS request
SOF interpolation function
SOF pulse output function
Three types of input clocks can built into the PLL and are available for selection
Input clocks of 48 MHz / 24 MHz / 12 MHz can be selected
Zero-Length packet addition function (DEZPM) when ending DMA transfers using the DEND pin
BRDY interrupt event notification timing change function (BFRE)
Function that automatically clears the buffer memory after the data for the pipe specified at the DxFIFO port has
been read (DCLRM)
Function to automatically supply a clock from the low-power sleep state (ATCKM)
NAK setting function for response PID generated by end of transfer (SHTNAK)
NAK response assignment function (NRDY)
1.2.8
Applications
Digital video cameras, digital still cameras, printers, external storage devices, portable information terminals, USB
audio devices
Also: GeneralOrdinary PC peripheral devices equipped with Hi-Speed USB