参数资料
型号: M66592WG
元件分类: 总线控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PBGA64
封装: 0.80 MM PITCH, FBGA-64
文件页数: 40/40页
文件大小: 1583K
代理商: M66592WG
M66592F P/W G
Rev 1.00 2004.10.01 page 9 of 125
1.6 Block diagram
The controller is configured with an analog front end unit (AFE), a protocol engine unit (Prtcl_Eng) that includes
an SIE, a pipe control unit (Pipe_Ctrl), a FIFO port unit (FIFO_Port), a buffer memory unit (Buf_Mem), an interrupt
control unit (Int_Ctrl), a bus interface unit (BIU), and a CPU interface register unit (CPU_IF_Reg). Figure 1.4 shows
a block diagram of the controller.
When data is being sent and received between the controller and a host controller connected on the USB bus, a
buffer memory assigned to each of the pipes is used. Two-way communication is possible by the controller changing
data stored in the buffer memory into USB data packets and outputting them to the USB bus using serial output, and
by inputting data packets on the USB bus which are then stored in the buffer memory.
A6(/ALE), A5-1,
D15-7, D6-1(/AD6-1), D0,
CS_N, RD_N,
WR0_N,WR1_N
MPBUS
CPU bus interface
INT_N, SOF_N
CPU_IF_Reg
Int_Ctrl
Interrupt /SOF output
I/O power supply
Core power supply
AFE power supply
Ground
AFE Ground
VDD
VIF
AFEA33V, AFED33V
AFEA15V, AFED15V
AFEA33G,AFED33G
AFEA15G,AFED15G
DGND
Buf_M
e
m
BIU
FIFO
_Port
Pipe_C
tr
l
P
rc
tl_
E
n
g
AFE
USB interface
SPLIT bus
SD7-0
DP, DM
DREQ0_N, DREQ1_N
DACK0_N,
DACK1_N/DSTB0_N,
DEND0_N, DEND1_N
DMA interafce
VBUS monitor input
VBUS
System control
RST_N, TEST
Renerence registor
REFRIN
Clock
XIN, XOUT
SIE
Figure 1.4 Block diagram
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