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参数资料
| 型号： | M66592WG |
| 元件分类： | 总线控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PBGA64 |
| 封装： | 0.80 MM PITCH, FBGA-64 |
| 文件页数： | 3/40页 |
| 文件大小： | 1583K |
| 代理商： | M66592WG |
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M66592F P/W G
Rev 1.00 2004.10.01 page 11 of 125
1.7.3
USB data transfers
The controller is capable of all types of transfers: USB communication control transfers, bulk transfers, and
interrupt transfers, as well as isochronous data transfers. The pipes noted below can be used with data transfers for
various types of communication.
(1) Dedicated control transfer pipe
(2) Two dedicated interrupt transfer pipes
(3) Three dedicated bulk transfer pipes
(4) Two pipes for which bulk transfers or isochronous transfers can be selected
The settings necessary for USB transfers, such as the transfer type, end point number, and maximum packet size,
should be set for each pipe, in conjunction with the user system.
Also, the controller has a built-in 5 kB buffer memory. For a dedicated bulk transfer pipe and the pipes for which
bulk transfers or isochronous transfers can be selected, settings such as the buffer memory assignment and buffer
operation mode which are based on the user system should be entered. The buffer operation mode setting can be set
to enable high-speed data transfers with few interrupts, using the double-buffer configuration and data packet
continuous transfer function.
Access to the buffer memory from the control CPU of the user’s system and the DMA controller is done through the
three FIFO port registers.
1.7.4
DMA interface
The DMA (Direct Memory Access) interface consists of data transfers between the user system and the controller
using the DxFIFO port, and is a type of data transfer in which the CPU is not involved. The controller is equipped
with a 2-channel DMA interface and has the following functions.
(1) A transfer end notification function using the Transfer End signal (DEND signal)
(2) An auto-clear function activated when a Zero-Length packet is received
(3) A “send addition” function used to send a Zero-Length packet based on input of the Transfer End signal (DEND
signal)
(4) A transfer end function using a transaction counter function
The controller supports the two types of DMA interfaces noted below.
(1) Cycle steal transfer
With this type of transfer, the DREQ pin is repeatedly asserted and negated each time a data transfer (1 byte /
1 word) is carried out.
(2) Burst transfer
With this type of transfer, the DREQ pin remains asserted for the pipe buffer area assigned to the pertinent
FIFO port, or until the transfer is ended by the DEND signal, without ever being negated.
Also, the following can be selected as the DMA interface handshake signal (pin): CS_N, RD_N, or WR_N, or
DACK_N. With DMA transfers using a split bus, high-speed DMA transfers are possible by changing the data setup
timing, by operating the OBUS bit of the DMAxCFG register.
1.7.5
SOF pulse output function
An SOF pulse output function is provided that notifies the system of the timing at which SOF packets are received.
This function outputs pulses at fairly regular intervals, using an SOF interpolation timer, even if an SOF packet is
damaged.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| M66592WG#RB0Z | 制造商:Renesas Electronics Corporation 功能描述:USB 2 Peripheral Controller 64-Pin FBGA 制造商:Renesas 功能描述:USB 2 Peripheral Controller 64-Pin FBGA |
| M66596FP | 制造商:Renesas Electronics Corporation 功能描述:USB CONTROLLERS |
| M66596FP#RB0Z | 制造商:Renesas Electronics Corporation 功能描述:MCU - Trays 制造商:Renesas Electronics 功能描述:USB Device Controller 64-Pin LQFP Cut Tape 制造商:Renesas Electronics 功能描述:USB Device Controller 64-Pin LQFP Tray 制造商:Renesas 功能描述:USB Device Controller 64-Pin LQFP |
| M66596FPRB0Z | 制造商:Renesas Electronics Corporation 功能描述:USB2.0 Dual Function Controller,LQFP64 |
| M66596WG | 制造商:RENESAS 制造商全称:Renesas Technology Corp 功能描述:ASSP (USB2.0 Dual Function Controller) |
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