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参数资料
| 型号： | M68LC302CPU20VCT |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 4 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100 |
| 封装： | 14 X 14 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, PLASITC, LQFP-100 |
| 文件页数： | 101/128页 |
| 文件大小： | 641K |
| 代理商： | M68LC302CPU20VCT |
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Signal Descriptions
MOTOROLA
MC68EN302 REFERENCE MANUAL
5-7
5.4.1 AMUX - DRAM Address Mux
The AMUX pin is an output only pin provided for implementing external address muxing
circuitry when accessing DRAM. The user may require use of this signal if external masters
are utilizing the EN302 DRAM controller. When performing an access to the EN302 as a
slave, the address is driven as an input, preventing the EN302 DRAM controller from driving
the address bus. Because of this, external muxing must take place. The AMUX pin is also
useful in implementations where a linear DRAM space is required.
The AMUX signal appears on the pin if the PM0 bit of the MBCTRL = 0. If PM0 = 1 then the
pin becomes BRG1 instead.
5.4.2 RAS0 - DRAM Row Address Select, Bit Zero
When the PM1 bit of the MBCTRL = 0, this active low output signal is used to select one of
two banks of DRAM as determined by the DRAM Base Address Register 0 (DBA0).
If PM1 = 1 then the pin becomes BRG2/SDS2/PA7 and is bidirectional depending on the
function chosen
5.4.3 RAS1 - DRAM Row Address Select Bit 1
When the PM2 bit of the MBCTRL = 0, this active low output signal is used to select one of
two banks of DRAM as determined by the DRAM Base Address Register1 (DBA1) CSR.
If PM2 = 1, then the pin is used as BRG3/PA12 and may be bidirectional
5.4.4 CAS0 - DRAM Column Address Select Bit 0
If the PM3 bit of the MBCTRL = 0, this active low output signal is used to enable the DRAM
module upper byte (bits 15–8).
If PM3 = 1 then the pin is used for PB0/IACK7 and may be bidirectional.
5.4.5 CAS1- DRAM Column Address Select Bit 1
If the PM4 bit of the MBCTRL = 0, this active low output signal is used to enable the lower
byte (bits 7–0) of the DRAM module.
If PM4 = 1 then the pin is used for PB1/IACK6 and may be bidirectional.
5.4.6 DRAMRW- DRAM Read/Write
If the PM5 bit of the MBCTRL = 0, this pin is asserted low for a DRAM write cycle. It is
separate from the processor bus R/W signal to allow precharge to take place without regard
to the state of R/W.
If PM5 = 1 then the pin is used for PB2/IACK1 and may be bidirectional.
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