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参数资料
| 型号： | M68LC302CPU20VCT |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 4 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100 |
| 封装： | 14 X 14 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, PLASITC, LQFP-100 |
| 文件页数： | 105/128页 |
| 文件大小： | 641K |
| 代理商： | M68LC302CPU20VCT |
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Signal Descriptions
5-11
MC68EN302 REFERENCE MANUAL
MOTOROLA
5.6.5 Address Mux (AMUX)
The AMUX pin is provided for implementing external address muxing circuitry so that
external masters may access DRAM modules controlled by the MC68EN302 DRAM
controller. External address muxing must take place in this situation since an access to the
MC68EN302 as a slave always results in the addresses driven as an input, and does not
output addresses to the DRAM module.
Another use for the AMUX pin would be implementations in which a linear DRAM space is
required.
5.6.6 Parity (PARITY1–PARITY0)
These two pins are provided to support parity checking of DRAM. If enabled, parity is
generated on writes and checked on reads. A parity error on a read generates a bus error.
PARITY0 is used in connection with D15-D8 and PARITY1 is used in connection with D7–
D0.
Parity checking/generation is not supported for external bus masters.
5.6.7 Muxing Scheme
To provide a simplified implementation of the Address Mux, a unique muxing scheme is
provided. Rather than providing programmability to change which addresses are muxed on
a particular signal, a generic muxing scheme is provided so that one muxing scheme may
be utilized by all supported DRAM bank sizes. Table 5-3 shows the DRAM muxing scheme.
The usage listed in the table is for typical operation. It is possible that some users may utilize
the Base Address Registers and the Mask bits in a non-standard way.
Table 5-3. Address Muxing Scheme
PROCESSOR
ADDRESS
ROW ADDRESS
COLUMN
ADDRESS
USAGE
A9
9
1
Used for all Bank Sizes
A10
10
2
A11
11
3
A12
12
4
A13
13
5
A14
14
6
A15
15
7
A16
16
8
A18
18
17
Used for 512K and up
A20
20
19
Used for 2M and up
A22
22
21
Used for 8M
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