
ETHERNET Controller
4-26
MC68EN302 REFERENCE MANUAL
MOTOROLA
Because each entry in the perfect-match table is 48 bits, but no more than 16 bits can be
written at a time; byte 5(or the word consisting of bytes 4 and 5 of a perfect-match entry)
must be written last. This prevents an address compare from occurring on partially-written
entries. When the first byte (or word) of an entry is written, that entry is temporarily disabled
until byte 5 (or a word consisting of bytes 4 and 5) is written.
The Address Recognition memory map for perfect match mode is shown in Figure 4-5. The
least significant bit of byte 0 (bit 8 of word MOBA + $A00, +$A08,...) corresponds to the I/G
address bit - this is the first bit received off the wire. The order of the bits received starts with
Byte 0-bit0 and continues through Byte0-bit7. The next byte is received as Byte1-bit0,
Byte1-bit1,...Byte1-bit7 up through byte 5.
Figure 4-5. AR Memory Map - Perfect Match Mode
When HASH_EN is set, the last two entries in the table are used for the logical address filter
mask bits. Hash index 0 is located in the least significant bit of byte 7 in the hash table
(MOBA + BFB). Hash index 63 is bit 7 of byte 0 (MOBA + BF0) in the hash table. When
writing logical address filter mask bits there is no restriction on the ordering of the writes.
When HASH_EN is set, the memory map is changed as shown in Figure 4-6. When
HASH_EN is set, locations MOBA + BF4, + BF6 AND MOBA + BFC, +BFE should not be
read or written to (DTACK will not be returned).
MOBA +$ A00
MOBA + $A02
MOBA + $A04
MOBA + $A06
BYTE 5
BYTE0
UNUSED
FIRST ENTRY
MOBA + $A08
MOBA + $A0A
MOBA + $A0C
MOBA + $A0E
BYTE 5
BYTE 0
UNUSED
SECOND ENTRY
MOBA + $BF8
MOBA + $BFA
MOBA + $BFC
MOBA + $BFE
BYTE 5
BYTE 0
UNUSED
LAST ENTRY
BYTE 1
BYTE 2
BYTE 3
BYTE 4