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| 型号： | M68LC302CPU20VCT |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 4 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100 |
| 封装： | 14 X 14 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, PLASITC, LQFP-100 |
| 文件页数： | 128/128页 |
| 文件大小： | 641K |
| 代理商： | M68LC302CPU20VCT |
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IEEE 1149.1 (JTAG) Test Access Port
7-14
MOTOROLA
7.4.4 CLAMP
The CLAMP instruction selects the single-bit bypass register as shown in Figure 7-11, and
the state of all signals driven from system output pins is completely defined by the data pre-
viously shifted into the boundary scan register (for example, using the SAMPLE/PRELOAD
instruction).
7.4.5 HI-Z
The HI-Z instruction is provided as a manufacturer’s optional public instruction to prevent
having to backdrive the output pins during circuit-board testing. When HI-Z is invoked, all
output drivers are turned off (i.e., high impedance). The instruction selects the bypass reg-
ister.
NOTE
On the MC68EN302, the THREESTATE pin may also be used
during system reset to perform the same function.
7.5 MC68EN302 RESTRICTIONS
The control afforded by the output enable signals using the boundary scan register and the
EXTEST instruction requires a compatible circuit-board test environment to avoid device-
destructive configurations. The user must avoid situations in which the MC68EN302 output
drivers are enabled into actively driven networks.
7.6 NON-SCAN CHAIN OPERATION
In non-scan chain operation, there are two constraints. First, the TCK input does not include
an internal pullup resistor and should not be left unconnected to preclude mid-level inputs.
The second constraint is to ensure that the scan chain test logic is kept transparent to the
system logic by forcing TAP into the test-logic-reset controller state. This is accomplished
by asserting the TRST signal during system reset (RESET and HALT asserted) and leaving
TMS unconnected or tied to VCC.
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