参数资料
型号: MAX11008BETM+
厂商: Maxim Integrated
文件页数: 62/67页
文件大小: 0K
描述: IC CTLR LDMOS BIAS DUAL 48TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 43
功能: 偏压控制器
RF 型: 手机
次要属性: 片上 4Kb EEPROM
封装/外壳: 48-WFQFN 裸露焊盘
包装: 托盘
Dual RF LDMOS Bias Controller with
Nonvolatile Memory
LOWI_ is set to 1 when the individual channel 1 and
channel 2 current-sense measurements exceed the
individual channel 1 and channel 2 low current thresh-
old and returns to 0 after the Flag register is read.
LOWI2 is replaced by LOWT2 when the INTEMP2 bit is
set in the Alarm Hardware Configuration register.
HIGHT_ is set to 1 when the individual channel 1 and
channel 2 temperature measurements exceed the indi-
vidual channel 1 and channel 2 high temperature
threshold and returns to 0 after the Flag register is
read. HIGHT2 is unused when the INTEMP2 bit is set in
the Alarm Hardware Configuration register. When
INTEMP2 is set, HIGHT2 returns a 1 or 0.
LOWT_ is set to 1 when the individual channel 1 and
channel 2 temperature measurements exceed the indi-
vidual channel 1 and channel 2 low temperature thresh-
old and returns to 0 after the Flag register is read.
LOWT2 is unused when the INTEMP2 bit is set in the
Alarm Hardware Configuration register. When INTEMP2
is set, LOWT2 returns a 1 or 0.
LUT Streaming Register (LUTSTRM) (Write Only)
Write to the LUT Streaming register to place the
MAX11008 into LUT streaming mode (see the LUT
Streaming Mode section and Table 27).
Bits LUTSL[7:0] specify the number of data words
(each data word is 16 bits long) that are to be written to
the EEPROM. The minimum and maximum number of
data words that can be written to the EEPROM are 1
and 256, respectively. Setting LUTSL[7:0] to 0 instructs
the MAX11008 to expect a LUT of length 1. Setting
Table 21. Software Shutdown Register
LUTSL[7:0] to 255 instructs the MAX11008 to expect a
LUT of length 256.
Bits LUTSA[7:0] specify the starting address of the data
that is to be written to the EEPROM. The MAX11008
counts the number of words that are written to the FIFO.
The device remains in LUT streaming mode until all the
indicated words are received.
Applications Information
External Temperature Sensor
Considerations
To optimize the performance of the temperature sen-
sors, place the MAX11008 as close as possible to the
remote diodes. Traces of DXP_ and DXN_ should not
be routed across noisy digital lines and buses.
Minimize the noise that is coupled into the DXP_ and
DXN_ traces by shielding them with ground traces on
each side of the pair of temperature sensor traces (see
Figure 23). Routing the DXP_ and DXN_ traces over the
analog ground plane (AGND) also helps minimize
noise. Use wide traces (10 mils or wider) to minimize
the trace inductance of the DXP_ and DXN_ traces.
Layout, Grounding, and Bypassing
Ensure that digital and analog signal lines are separat-
ed from each other. Use separate ground planes for
AGND and DGND. Connect both ground planes to a
single point on the PCB (star ground point). Do not run
analog and digital signals parallel to one another
(especially clock signals), and do not run digital lines
underneath the MAX11008 package. High-frequency
noise in the AV DD power supply may affect performance.
DATA BITS
D[15:6]
D5
BIT NAME
Unused
FULLPD
RESET STATE
X
0
FUNCTION
Unused bits.
Full power-down bit. Set to 1 to power down all sections of the MAX11008.
Set to 0 to exit full power-down mode.
Reference power-on bit. Set to 1 to force internal voltage reference to
D4
FBGON
0
remain on at all times (except when FULLPD is set to 1). Set to 0 to only
power internal reference when an ADC conversion is performed.
D3
D2
D1
D0
WDGPD
OSCPD
DAC2PD
DAC1PD
0
0
1
1
Watchdog oscillator power-down bit. Set to 1 to power down internal
watchdog oscillator.
Internal oscillator power-down bit. Set to 1 to power down internal oscillator.
Channel 2 DAC power-down bit. Set to 1 to power down DAC2 and PGA2.
Channel 1 DAC power-down bit. Set to 1 to power down DAC1 and PGA1.
X = Don’t care.
62
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