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参数资料
| 型号： | MAX16068ETI+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 19/41页 |
| 文件大小： | 0K |
| 描述： | IC SYSTEM MANAGER 6CH 28-TQFN |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 应用： | 六路电源监控器 |
| 电源电压： | 2.8 V ~ 14 V |
| 电流 - 电源： | 2.8mA |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-WFQFN 裸露焊盘 |
| 供应商设备封装： | 28-TQFN-EP（5x5） |
| 包装： | 带卷 (TR) |
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6-Channel, Flash-Configurable System Manager
with Nonvolatile Fault Registers
Set r74h[4:3] to a value other than ‘00’ to select autoretry
mode (see Table 14). In this configuration, the device
stops monitoring after a critical fault event then moni-
tors again following the boot-up delay plus 20ms (see
the Boot-Up Delay section). Use r74h[2:0] to select an
autoretry delay from 20ms to 1.6s. See Table 14 for more
information on setting the autoretry delay.
When fault information is stored in flash (see the Critical
Faults section) and autoretry mode is selected, set an
autoretry delay greater than the time required for the
storing operation. When fault information is stored in
flash and latch-on-fault mode is chosen, toggle EN or
reset the software enable bit only after the completion
of the storing operation. When saving information about
the failed lines only, ensure a delay of at least 102ms
before the restart procedure. Otherwise, ensure a mini-
mum 153ms timeout, to ensure that ADC conversions
are completed and values are stored correctly in flash.
Reset Output
The reset output, RESET, indicates the status of the
monitored inputs. It asserts during the boot phase and
deasserts following the reset timeout period once the
monitored input voltage is within the undervoltage/over-
voltage.
During normal monitoring, RESET can be configured to
assert when any combination of MON_ inputs violates
configurable combinations of undervoltage or overvolt-
age thresholds. Select the combination of MON_ inputs
using r3Ch[5:0] and r3Dh[5:0]. Note that MON_ inputs
configured as critical faults always cause RESET to
assert regardless of these configuration bits.
RESET can be configured as push-pull or open drain
using r3Bh[3], and active high or active low using
r3Bh[2]. Select the reset timeout by loading a value from
Table 15 into r3Bh[7:4].
To generate a one-shot pulse on RESET, write a ‘1’ into
r3Bh[0]. The pulse width is the configured reset timeout.
Register bit r3Bh[0] clears automatically (see Table 15).
The current state of RESET can be checked by reading
r20h[0].
Table 14. Autoretry Configuration
REGISTER
ADDRESS
FLASH
ADDRESS
BIT
RANGE
DESCRIPTION
Retry Delay
000 = 20ms
001 = 40ms
010 = 80ms
[2:0]
011 = 150ms
100 = 280ms
74h
274h
[4:3]
101 = 540ms
110 = 1s
111 = 2s
Autoretry/Latch Mode
00 = Latch
01 = Retry 1 time
10 = Retry 3 times
11 = Always retry
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