参数资料
型号: MAX16068ETI+T
厂商: Maxim Integrated Products
文件页数: 24/41页
文件大小: 0K
描述: IC SYSTEM MANAGER 6CH 28-TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
应用: 六路电源监控器
电源电压: 2.8 V ~ 14 V
电流 - 电源: 2.8mA
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 28-WFQFN 裸露焊盘
供应商设备封装: 28-TQFN-EP(5x5)
包装: 带卷 (TR)
6-Channel, Flash-Configurable System Manager
with Nonvolatile Fault Registers
A master device communicates to the MAX16068 by
transmitting the proper address followed by command
and/or data words. The slave address input, A0, is
capable of detecting four different states, allowing mul-
tiple identical devices to share the same serial bus. The
slave address is described further in the Slave Address
section. Each transmit sequence is framed by a START
(S) or REPEATED START (Sr) condition and a STOP (P)
condition. Each word transmitted over the bus is 8 bits
long and is always followed by an acknowledge pulse.
SCL is a logic input, while SDA is an open-drain input/
output. SCL and SDA both require external pullup resis-
tors to generate the logic-high voltage. Use 4.7k I for
most applications.
Bit Transfer
Each clock pulse transfers one data bit. The data on
SDA must remain stable while SCL is high (Figure 6);
otherwise, the MAX16068 registers a START or STOP
condition (Figure 7) from the master. SDA and SCL idle
high when the bus is not busy.
START and STOP Conditions
A master device signals the beginning of a transmission
with a START condition by transitioning SDA from high to
low while SCL is high. The master device issues a STOP
condition by transitioning SDA from low to high while
SCL is high. A STOP condition frees the bus for another
transmission. The bus remains active if a REPEATED
START condition is generated, such as in the block read
protocol (see Figure 1, SMBus Timing Diagram).
Early STOP Conditions
The MAX16068 recognizes a STOP condition at any point
during transmission except if a STOP condition occurs in
the same high pulse as a START condition. This condition
is not a legal SMBus format; at least one clock pulse must
separate any START and STOP condition.
REPEATED START Conditions
A REPEATED START can be sent instead of a STOP
condition to maintain control of the bus during a read
operation. The START and REPEATED START conditions
are functionally identical.
SDA
SDA
SCL
SCL
S
P
DATA LINE STABLE,
DATA VALID
Figure 6. Bit Transfer
CHANGE OF
DATA ALLOWED
START
CONDITION
Figure 7. START and STOP Conditions
STOP
CONDITION
24
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