参数资料
型号: MAX16068ETI+T
厂商: Maxim Integrated Products
文件页数: 28/41页
文件大小: 0K
描述: IC SYSTEM MANAGER 6CH 28-TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
应用: 六路电源监控器
电源电压: 2.8 V ~ 14 V
电流 - 电源: 2.8mA
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 28-WFQFN 裸露焊盘
供应商设备封装: 28-TQFN-EP(5x5)
包装: 带卷 (TR)
6-Channel, Flash-Configurable System Manager
with Nonvolatile Fault Registers
9)
The slave sends an 8-bit data byte.
3)
The addressed slave asserts an ACK on SDA.
10) The master asserts a NACK on SDA.
11) The master sends a STOP condition.
If the memory address is not valid, it is NACKed by the
slave at step 5 and the address pointer is not modified.
When PEC is enabled, the Read Byte protocol becomes:
4)
5)
6)
The master sends the 8-bit command code for block
write (A5h).
The addressed slave asserts an ACK on SDA.
The master sends the 8-bit byte count (1 byte to 16
bytes), n.
1)
2)
The master sends a START condition.
The master sends the 7-bit slave ID plus a write bit
(low).
7)
8)
9)
The addressed slave asserts an ACK on SDA.
The master sends 8 bits of data.
The addressed slave asserts an ACK on SDA.
3)
4)
The addressed slave asserts an ACK on the data
line.
The master sends 8-bit memory address.
10) Repeat steps 8 and 9 n - 1 times.
11) The master sends a STOP condition.
When PEC is enabled, the Block Write protocol becomes:
5)
6)
7)
8)
9)
The active slave asserts an ACK on the data line.
The master sends a REPEATED START condition.
The master sends the 7-bit slave ID plus a read bit
(high).
The addressed slave asserts an ACK on the data
line.
The slave sends 8 data bits.
1)
2)
3)
4)
The master sends a START condition.
The master sends the 7-bit slave ID plus a write bit
(low).
The addressed slave asserts an ACK on the data
line.
The master sends 8 bits of the block write command
code.
10) The master asserts an ACK on the data line.
11) The slave sends an 8-bit PEC byte.
12) The master asserts a NACK on the data line.
13) The master generates a STOP condition.
Block Write
5)
6)
7)
8)
9)
The slave asserts an ACK on the data line.
The master sends 8 bits byte count (min 1, max 16) n.
The slave asserts an ACK on the data line.
The master sends 8 bits of data.
The slave asserts an ACK on the data line.
The block write protocol (see Figure 9) allows the master
device to write a block of data (1–16 bytes) to memory.
Preload the destination address by a previous send byte
command; otherwise the block write command begins to
write at the current address pointer. After the last byte
is written, the address pointer remains preset to the
next valid address. If the number of bytes to be written
causes the address pointer to exceed 8Fh for configura-
tion registers or configuration flash or FFh for user flash,
the address pointer stays at 8Fh or FFh, respectively,
overwriting this memory address with the remaining
bytes of data. The slave generates a NACK at step 5 if
the command code is invalid or if the device is busy, and
the address pointer is not altered.
The block write procedure is as follows:
10) Repeat 8 and 9 n - 1 times.
11) The master sends an 8-bit PEC byte.
12) The slave asserts an ACK on the data line (if PEC is
good, otherwise NACK).
13) The master generates a STOP condition.
Block Read The block read protocol (see Figure 9)
allows the master device to read a block of up to 16
bytes from memory. Read fewer than 16 bytes of data
by issuing an early STOP condition from the master, or
by generating a NACK with the master. The destination
address should be preloaded by a previous send byte
command; otherwise, the block read command begins
to read at the current address pointer. If the number of
bytes to be read causes the address pointer to exceed
1)
2)
The master sends a START condition.
The master sends the 7-bit slave address and a
write bit (low).
8Fh for the configuration register or configuration flash
or FFh in user flash, the address pointer stays at 8Fh or
FFh, respectively.
The block read procedure is the following:
28
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