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| 型号： | MAX16068ETI+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 33/41页 |
| 文件大小： | 0K |
| 描述： | IC SYSTEM MANAGER 6CH 28-TQFN |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 应用： | 六路电源监控器 |
| 电源电压： | 2.8 V ~ 14 V |
| 电流 - 电源： | 2.8mA |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-WFQFN 裸露焊盘 |
| 供应商设备封装： | 28-TQFN-EP（5x5） |
| 包装： | 带卷 (TR) |
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6-Channel, Flash-Configurable System Manager
with Nonvolatile Fault Registers
Exit1-IR: A rising edge on TCK with TMS low puts the
controller in the pause-IR state. If TMS is high on the ris-
ing edge of TCK, the controller enters the update-IR state.
Pause-IR: Shifting of the instruction shift register halts
temporarily. With TMS high, a rising edge on TCK puts
the controller in the exit2-IR state. The controller remains
in the pause-IR state if TMS is low during a rising edge
on TCK.
Exit2-IR: A rising edge on TCK with TMS high puts the
controller in the update-IR state. The controller loops
back to shift-IR if TMS is low during a rising edge of TCK
in this state.
Update-IR: The instruction code that has been shifted
into the instruction shift register latches to the parallel
outputs of the instruction register on the falling edge of
TCK as the controller enters this state. Once latched,
this instruction becomes the current instruction. A rising
edge on TCK with TMS low puts the controller in the run-
test/idle state. With TMS high, the controller enters the
select-DR-scan state.
Instruction Register
The instruction register contains a shift register as well
as a latched 5-bit wide parallel output. When the TAP
controller enters the shift-IR state, the instruction shift
register connects between TDI and TDO. While in the
Table 21. JTAG Instruction Set
shift-IR state, a rising edge on TCK with TMS low shifts
the data one stage toward the serial output at TDO. A
rising edge on TCK in the exit1-IR state or the exit2-IR
state with TMS high moves the controller to the update-
IR state. The falling edge of that same TCK latches the
data in the instruction shift register to the instruction
register parallel output. Table 21 shows the instructions
supported by the MAX16068 and the respective opera-
tional binary codes.
BYPASS: When the BYPASS instruction is latched into
the instruction register, TDI connects to TDO through the
1-bit bypass test data register. This allows data to pass
from TDI to TDO without affecting the device’s operation.
IDCODE: When the IDCODE instruction is latched into
the parallel instruction register, the identification data
register is selected. The device identification code is
loaded into the identification data register on the rising
edge of TCK following entry into the capture-DR state.
Shift-DR can be used to shift the identification code
out serially through TDO. During test-logic-reset, the
IDCODE instruction is forced into the instruction register.
The identification code always has a ‘1’ in the LSB posi-
tion. The next 11 bits identify the manufacturer’s JEDEC
number and number of continuation bytes followed by
16 bits for the device and 4 bits for the version. See
Table 22.
INSTRUCTION
BYPASS
IDCODE
USERCODE
LOAD ADDRESS
READ DATA
WRITE DATA
REBOOT
SAVE
SETFLSHADD
RSTFLSHADD
SETUSRFLSH
RSTUSRFLSH
CODE
0x1F
0x00
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
NOTES
Mandatory instruction code
Load manufacturer ID code/part number
Load user code
Load address register content
Read data pointed by current address
Write data pointed by current address
Reboot FLASH data content into register file
Trigger emergency save to flash
Flash page access ON
Flash page access OFF
User flash access ON (must be in flash page already)
User flash access OFF (return to flash page)
Table 22. 32-Bit Identification Code
MSB
LSB
VERSION (4 BITS)
0001
PART NUMBER (16 BITS)
1000000000000010
MANUFACTURER (11 BITS)
00011001011
FIXED VALUE (1 BIT)
1
______________________________________________________________________________________
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