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| 型号： | MAX16068ETI+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 32/41页 |
| 文件大小： | 0K |
| 描述： | IC SYSTEM MANAGER 6CH 28-TQFN |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 应用： | 六路电源监控器 |
| 电源电压： | 2.8 V ~ 14 V |
| 电流 - 电源： | 2.8mA |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-WFQFN 裸露焊盘 |
| 供应商设备封装： | 28-TQFN-EP（5x5） |
| 包装： | 带卷 (TR) |
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6-Channel, Flash-Configurable System Manager
with Nonvolatile Fault Registers
1
TEST-LOGIC-RESET
0
0
RUN-TEST/IDLE
1
SELECT-DR-SCAN
1
SELECT-IR-SCAN
1
0
0
1
CAPTURE-DR
0
1
CAPTURE-IR
0
SHIFT-DR
1
EXIT1-DR
0
PAUSE-DR
1
0
1
0
SHIFT-IR
1
EXIT1-IR
0
PAUSE-IR
1
0
1
0
0
1
EXIT2-DR
1
UPDATE-DR
0
0
1
EXIT2-IR
1
UPDATE-IR
0
Figure 11. Tap Controller State Diagram
Pause-DR: Shifting of the test data registers halts while
in this state. All test data registers retain their previous
state. The controller remains in this state while TMS is
low. A rising edge on TCK with TMS high puts the con-
troller in the exit2-DR state.
Exit2-DR: A rising edge on TCK with TMS high while in
this state puts the controller in the update-DR state. A ris-
ing edge on TCK with TMS low enters the shift-DR state.
Update-DR: A falling edge on TCK while in the update-
DR state latches the data from the shift register path of
the test data registers into a set of output latches. This
prevents changes at the parallel output because of
changes in the shift register. On the rising edge of TCK,
the controller goes to the run-test/idle state if TMS is low
or goes to the select-DR-scan state if TMS is high.
Select-IR-Scan: All test data registers retain the previ-
ous states. The instruction register remains unchanged
during this state. With TMS low, a rising edge on TCK
moves the controller into the capture-IR state. TMS high
during a rising edge on TCK puts the controller back into
the test-logic-reset state.
Capture-IR: Use the capture-IR state to load the shift
register in the instruction register with a fixed value.
This value is loaded on the rising edge of TCK. If TMS is
high on the rising edge of TCK, the controller enters the
exit1-IR state. If TMS is low on the rising edge of TCK,
the controller enters the shift-IR state.
Shift-IR: In this state, the shift register in the instruction
register connects between TDI and TDO and shifts data
one stage for every rising edge of TCK toward the TDO
serial output while TMS is low. The parallel outputs of
the instruction register as well as all test data registers
remain at the previous states. A rising edge on TCK with
TMS high moves the controller to the exit1-IR state. A
rising edge on TCK with TMS low keeps the controller in
the shift-IR state while moving data one stage through
the instruction shift register.
32
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