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参数资料
| 型号： | MAX16068ETI+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 34/41页 |
| 文件大小： | 0K |
| 描述： | IC SYSTEM MANAGER 6CH 28-TQFN |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 应用： | 六路电源监控器 |
| 电源电压： | 2.8 V ~ 14 V |
| 电流 - 电源： | 2.8mA |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-WFQFN 裸露焊盘 |
| 供应商设备封装： | 28-TQFN-EP（5x5） |
| 包装： | 带卷 (TR) |
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6-Channel, Flash-Configurable System Manager
with Nonvolatile Fault Registers
USERCODE: When the USERCODE instruction latches
into the parallel instruction register, the user-code data
register is selected. The device user-code loads into the
user-code data register on the rising edge of TCK fol-
lowing entry into the capture-DR state. Shift-DR can be
used to shift the user-code out serially through TDO. See
Table 24. This instruction can be used to help identify
multiple MAX16068 devices connected in a JTAG chain.
LOAD ADDRESS: This is an extension to the standard
IEEE 1149.1 instruction set to support access to the
memory in the MAX16068. When the LOAD ADDRESS
instruction latches into the instruction register, TDI con-
nects to TDO through the 8-bit memory address test
data register during the shift-DR state.
READ DATA: This is an extension to the standard IEEE
1149.1 instruction set to support access to the memory
in the MAX16068. When the READ DATA instruction
latches into the instruction register, TDI connects to TDO
through the 8-bit memory read test data register during
the shift-DR state.
WRITE DATA: This is an extension to the standard IEEE
1149.1 instruction set to support access to the memory
in the MAX16068. When the WRITE DATA instruction
latches into the instruction register, TDI connects to TDO
through the 8-bit memory write test data register during
the shift-DR state.
REBOOT: This is an extension to the standard IEEE
1149.1 instruction set to initiate a software-controlled
reset to the MAX16068. When the REBOOT instruc-
tion latches into the instruction register, the MAX16068
resets and immediately begins the boot-up sequence.
SAVE: This is an extension to the standard IEEE 1149.1
instruction set that triggers a fault log. The current ADC
conversion results along with fault information are saved
to flash depending on the configuration of the Critical
Fault Log Control register (r6Dh).
SETFLSHADD: This is an extension to the standard
IEEE 1149.1 instruction set that allows access to the
flash page. Flash registers include ADC conversion
results and GPIO_ input/output data. Use this page to
access registers 200h–2FFh.
RSTFLSHADD: This is an extension to the standard
IEEE 1149.1 instruction set. Use RSTFLSHADD to return
to the default page and disable access to the flash page.
SETUSRFLSH: This is an extension to the standard
IEEE 1149.1 instruction set that allows access to the user
flash page. When on the configuration flash page, send
the SETUSRFLSH command, all addresses are recog-
nized as flash addresses only. Use this page to access
registers 300h–3FFh.
RSTUSRFLSH: This is an extension to the standard
IEEE 1149.1 instruction set. Use RSTUSRFLSH to return
to the configuration flash page and disable access to
the user flash.
Restrictions When Writing to Flash
Flash must be written to 8 bytes at a time. The initial
address must be aligned to 8-byte boundaries—the 3
LSBs of the initial address must be ‘000’. Write the 8
bytes using eight successive WRITE DATA commands.
A write operation requires 122ms for each 8-byte block.
After programming a block, check r20h[1] (see Table
25) to make sure the write operation is complete before
attempting to write the next block.
Table 23. 32-Bit User-Code Data
MSB
LSB
DON’T CARE
00000000000000000
Table 24. Maximu m Write Time
See Table 18
SMBUS SLAVE ID
USER ID (r8Ah[7:0])
r6Dh[1:0] VALUE
00
01
10
11
DESCRIPTION
Save flags and ADC readings
Save flags
Save ADC readings
Do not save anything
MAXIMUM WRITE TIME (ms)
153
102
153
—
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