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参数资料
| 型号： | MAX17482GTL+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 10/48页 |
| 文件大小： | 0K |
| 描述： | IC CTLR PWM DUAL IMVP-6.5 40TQFN |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 系列： | Quick-PWM™ |
| 应用： | 控制器，Intel IMVP-6，IMVP-6.5? |
| 输入电压： | 4.5 V ~ 5.5 V |
| 输出数： | 1 |
| 输出电压： | 0.013 V ~ 1.5 V |
| 工作温度： | -40°C ~ 105°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 40-WFQFN 裸露焊盘 |
| 供应商设备封装： | 40-TQFN-EP（5x5） |
| 包装： | 带卷 (TR) |
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Dual-Phase, Quick-PWM Controllers for
IMVP-6+/IMVP-6.5 CPU Core Power Supplies
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, V IN = 10V, V CC = V DD = V SHDN = V PGDIN = V PSI = V ILIM = 5V, V3P3 = 3.3V, DPRSLPVR = GNDS = GND, V CSP1
= V CSN1 = V CSP2 = V CSN2 = 1.0000V, FB = FBAC, R FBAC = 3.57k Ω from FBAC to CSN1, D6–D0 = [0101000]; MAX17082/MAX17482:
V SLOW = 5V; MAX17021: DPRSTP = GND; T A = -40°C to +105°C , unless otherwise noted.) (Note 4)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
VALLEY CURRENT LIMIT, DROOP, AND CURRENT BALANCE
Current-Limit Threshold
Voltage (Positive)
V LIMIT
V CSP_ - V CSN_
V TIME - V ILIM = 100mV
V TIME - V ILIM = 500mV
7
40
13
60
mV
ILIM = V CC
19
26
CSP_, CSN_ Common-Mode
Input Range
0
2
V
Droop Amplifier
Transconductance
Current-Balance Amplifier
Offset
G m(FBAC)
I FBAC / [ (V CSP_ - V CSN_ )],
indicates summation over all phases from 1 to
N, N = 2, V FBAC = V CSN- = 0.45V to 2V
(V CSP1 - V CSN1 ) - (V CSP2 - V CSN2 ) at I CCI = 0
585
-1.25
610
+1.25
μS
mV
CURRENT MONITOR (MAX17082/MAX17482 Only)
Current-Monitor
Transconductance
IMON Clamp Voltage
G m(IMON)
V IMON,max
I IMON / [ (V CSP_ - V CSN_ )],
indicates summation over all phases from 1 to
N, N = 2, V CSN_ = 0.45V to 2V
I SINK = 10mA
2.2
1.05
2.6
1.15
mS
V
GATE DRIVERS
DH_ Gate Driver
On-Resistance
DL_ Gate Driver
On-Resistance
R ON(DH_)
R ON(DL_)
BST_ - LX_ forced to 5V
High state (pullup)
Low state (pulldown)
High state (pullup)
Low state (pulldown)
2.5
2.0
2.0
0.7
LOGIC AND I/O
Logic Input High Voltage
Logic Input Low Voltage
Low-Voltage Logic Input
High Voltage
Low-Voltage Logic Input
Low Voltage
V IH
V IL
V IHLV
V ILLV
SHDN , PGDIN:
MAX17021: DPRSLPVR
SHDN , PGDIN:
MAX17021: DPRSLPVR
PSI , D0 –D6:
MAX17082/MAX17482: DPRSLPVR, SLOW
MAX17021: DPRSTP
PSI , D0 –D6:
MAX17082/MAX17482: DPRSLPVR, SLOW
MAX17021: DPRSTP
2.3
0.67
1.0
0.33
V
V
V
V
Note 2: When pulse skipping, the output rises by approximately 1.5% when transitioning from continuous conduction to no load.
Note 3: On-time and minimum off-time specifications are measured from 50% to 50% at the DH_ and DL_ pins, with LX_ forced to
GND, BST_ forced to 5V, and a 500pF capacitor from DH_ to LX_ to simulate external MOSFET gate capacitance. Actual in-
circuit times might be different due to MOSFET switching speeds.
Note 4: Specifications to T A = -40°C and +105°C are guaranteed by design and are not production tested.
10
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