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参数资料
| 型号： | MAX17482GTL+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 38/48页 |
| 文件大小： | 0K |
| 描述： | IC CTLR PWM DUAL IMVP-6.5 40TQFN |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 系列： | Quick-PWM™ |
| 应用： | 控制器，Intel IMVP-6，IMVP-6.5? |
| 输入电压： | 4.5 V ~ 5.5 V |
| 输出数： | 1 |
| 输出电压： | 0.013 V ~ 1.5 V |
| 工作温度： | -40°C ~ 105°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 40-WFQFN 裸露焊盘 |
| 供应商设备封装： | 40-TQFN-EP（5x5） |
| 包装： | 带卷 (TR) |
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Dual-Phase, Quick-PWM Controllers for
IMVP-6+/IMVP-6.5 CPU Core Power Supplies
Power-Up Sequence (POR, UVLO)
The MAX17021/MAX17082/MAX17482 are enabled
when SHDN is driven high (Figure 10). The internal ref-
erence powers up first. Once the reference exceeds its
UVLO threshold, the internal analog blocks are turned
on and masked by a 50μs one-shot delay. The PWM
controller is then enabled.
Power-on reset (POR) occurs when V CC rises above
approximately 2V, resetting the fault latch and prepar-
ing the controller for operation. The V CC UVLO circuitry
inhibits switching until V CC rises above 4.25V. The con-
troller powers up the reference once the system
enables the controller, V CC is above 4.25V, and SHDN
is driven high. With the reference in regulation, the con-
troller ramps the output voltage to the boot voltage
(1.2V for MAX17021 IMVP-6+ and 1.1V for MAX17082/
MAX17482 IMVP-6.5) at 1/8 the slew rate set by R TIME :
current limit, so full output current is available immediate-
ly. CLKEN is pulled low approximately 60μs after the
MAX17021/MAX17082/MAX17482 reach the boot voltage
if PGDIN is high. At the same time, the MAX17021/
MAX17082/MAX17482 slew the output to the voltage set
at the VID inputs at the programmed slew rate. PWRGD
and PHASEGD become high impedance approximately
5ms after CLKEN is pulled low. The MAX17021/
MAX17082/MAX17482 automatically use forced-PWM
operation during soft-start and soft-shutdown, regardless
of the DPRSLPVR and PSI configuration.
For automatic startup, the battery voltage should be
present before V CC . If the controller attempts to bring
the output into regulation without the battery voltage
present, the fault latch trips. The controller remains shut
down until the fault latch is cleared by toggling SHDN
or cycling the V CC power supply below 0.5V.
t TRAN ( START ) =
8 V BOOT
( dV TARGET dt )
If the V CC voltage drops below 4.25V, the controller
assumes that there is not enough supply voltage to
make valid decisions. To protect the output from over-
where dV TARGET /dt = 12.5mV/μs x 71.5k Ω /R TIME is the
slew rate. The soft-start circuitry does not use a variable
V CC
SHDN
voltage faults, the controller shuts down immediately
and forces a high-impedance output.
VID (D0–D6)
SOFT-START =
1/8 SLEW RATE SET
INVALID
CODE
V BOOT
INVALID
CODE
SOFT-SHUTDOWN =
1/8 SLEW RATE SET
V CORE
INTERNAL
BY R TIME
BY R TIME
PWM CONTROL
SKIP
FORCED PWM
FORCED PWM
PHASEGD
CLKEN
PWRGD
t BLANK
60 μ s TYP
t BLANK
20 μ s TYP
t BLANK
5ms TYP
t BLANK
60 μ s TYP
Figure 10. Power-Up and Shutdown Sequence Timing Diagram
38
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