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参数资料
| 型号： | MAX17482GTL+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 47/48页 |
| 文件大小： | 0K |
| 描述： | IC CTLR PWM DUAL IMVP-6.5 40TQFN |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 系列： | Quick-PWM™ |
| 应用： | 控制器，Intel IMVP-6，IMVP-6.5? |
| 输入电压： | 4.5 V ~ 5.5 V |
| 输出数： | 1 |
| 输出电压： | 0.013 V ~ 1.5 V |
| 工作温度： | -40°C ~ 105°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 40-WFQFN 裸露焊盘 |
| 供应商设备封装： | 40-TQFN-EP（5x5） |
| 包装： | 带卷 (TR) |
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Dual-Phase, Quick-PWM Controllers for
IMVP-6+/IMVP-6.5 CPU Core Power Supplies
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Keep the high-current, gate-driver traces (DL_,
DH_, LX_, and BST_) short and wide to minimize
trace resistance and inductance. This is essential
for high-power MOSFETs that require low-imped-
ance gate drivers to avoid shoot-through currents.
CSP_ and CSN_ connections for current limiting
and voltage positioning must be made using Kelvin-
sense connections to guarantee the current-sense
accuracy.
When trade-offs in trace lengths must be made, it is
preferable to allow the inductor charging path to be
made longer than the discharge path. For example,
it is better to allow some extra distance between the
input capacitors and the high-side MOSFET than to
allow distance between the inductor and the low-
side MOSFET or between the inductor and the out-
put filter capacitor.
Route high-speed switching nodes away from sen-
sitive analog areas (CCI, FB, CSP_, CSN_, etc.).
3) Group the gate-drive components (BST_ diodes
and capacitors, V DD bypass capacitor) together
near the controller IC.
4) Make the DC-DC controller ground connections as
shown in Figures 1 and 2. This diagram can be
viewed as having four separate ground planes:
input/output ground, where all the high-power com-
ponents go; the power ground plane, where the
GND pin and V DD bypass capacitor go; the mas-
ter’s analog ground plane where sensitive analog
components go, the master’s GND pin and V CC
bypass capacitor go; and the slave ’s analog
ground plane where the slave’s GND pin and V CC
bypass capacitor go. The master’s GND plane must
meet the GND plane only at a single point directly
beneath the IC. Similarly, the slave’s GND plane
must meet the GND plane only at a single point
directly beneath the IC. The respective master and
slave ground planes should connect to the high-
power output ground with a short metal trace from
Layout Procedure
1) Place the power components first, with ground ter-
minals adjacent (low-side MOSFET source, C IN ,
C OUT , and D1 anode). If possible, make all these
connections on the top layer with wide, copper-
filled areas.
2) Mount the controller IC adjacent to the low-side
MOSFET. The DL_ gate traces must be short and
wide (50 mils to 100 mils wide if the MOSFET is 1in
from the controller IC).
Chip Information
PROCESS: BiCMOS
GND to the source of the low-side MOSFET (the
middle of the star ground). This point must also be
very close to the output capacitor ground terminal.
5) Connect the output power planes (V CORE and sys-
tem ground planes) directly to the output filter
capacitor positive and negative terminals with multi-
ple vias. Place the entire DC-DC converter circuit as
close to the CPU as is practical.
Package Information
For the latest package outline information and land patterns, go
to www.maxim-ic.com/packages .
PACKAGE TYPE
40 TQFN-EP
PACKAGE CODE
T4055-2
DOCUMENT NO.
21-0140
______________________________________________________________________________________
47
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