参数资料
型号: MAX17482GTL+T
厂商: Maxim Integrated Products
文件页数: 36/48页
文件大小: 0K
描述: IC CTLR PWM DUAL IMVP-6.5 40TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
系列: Quick-PWM™
应用: 控制器,Intel IMVP-6,IMVP-6.5?
输入电压: 4.5 V ~ 5.5 V
输出数: 1
输出电压: 0.013 V ~ 1.5 V
工作温度: -40°C ~ 105°C
安装类型: 表面贴装
封装/外壳: 40-WFQFN 裸露焊盘
供应商设备封装: 40-TQFN-EP(5x5)
包装: 带卷 (TR)
Dual-Phase, Quick-PWM Controllers for
IMVP-6+/IMVP-6.5 CPU Core Power Supplies
CPU FREQ
CPU LOAD
VID (D0–D6)
CPU CORE
VOLTAGE
PSI
INTERNAL
PWM CONTROL
PWRGD
CLKEN
2-PHASE PWM
BLANK HIGH IMPEDANCE
BLANK LOW
1-PHASE PWM
2-PHASE PWM
BLANK HIGH IMPEDANCE
BLANK LOW
PHASEGD
t BLANK
20 μ s typ
BLANK HIGH IMPEDANCE
t BLANK
20 μ s typ
32 SWITCHING CYCLES ON DH2
Figure 8. PSI Transition
P S I Transitions
When PSI is pulled low, the MAX17021/MAX17082/
MAX17482 immediately disable phase 2 (DH2 and DL2
forced low), blank PHASEGD high impedance, and
enter single-phase PWM operation (see Figure 8).
When PSI is pulled high, the MAX17021/MAX17082/
MAX17482 enable phase 2. PHASEGD is blanked high
impedance for 32 switching cycles on DH2, allowing
sufficient time/cycles for phases 1 and 2 to achieve cur-
rent balance. In a typical IMVP-6 application, the VID is
reduced by 1 LSB (12.5mV) when PSI is pulled low,
and increased by 1 LSB when PSI is pulled high.
Forced-PWM Operation (Normal Mode)
During soft-shutdown, and normal operation—when the
CPU is actively running (DPRSLPVR = low) —the
MAX17021/MAX17082/MAX17482 operate with the low-
noise, forced-PWM control scheme. Forced-PWM oper-
ation disables the zero-crossing comparators of all
active phases, forcing the low-side gate-drive wave-
forms to constantly be the complement of the high-side
gate-drive waveforms. This keeps the switching fre-
quency constant and allows the inductor current to
reverse under light loads, providing fast, accurate neg-
ative output-voltage transitions by quickly discharging
the output capacitors.
Forced-PWM operation comes at a cost: the no-load 5V
bias supply current remains between 10mA to 50mA
per phase, depending on the external MOSFETs and
switching frequency. To maintain high efficiency under
light-load conditions, the processor can switch the con-
troller to a low-power pulse-skipping control scheme
after entering suspend mode.
PSI determines how many phases are active when
operating in forced-PWM mode (DPRSLPVR = low).
When PSI is pulled low, the main phase remains active
but the secondary phase is disabled (DH2 and DL2
forced low).
36
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